A Low-Latency, Low-Area Hardware Oblivious RAM Controller

A Low-Latency, Low-Area Hardware Oblivious RAM Controller

We build and evaluate Tiny ORAM, an Oblivious RAM prototype on FPGA. Oblivious RAM is a cryptographic primitive that completely obfuscates an application’s data, access pattern, and read/write behavior to/from external memory (such as DRAM or disk). Tiny ORAM makes two main contributions. First, by...

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Bibliographic Details
Main Authors: Fletcher, Christopher Wardlaw, Ren, Ling, Kwon, Young Hyun, van Dijk, Marten, Stefanov, Emil, Serpanos, Dimitrios, Devadas, Srinivas
Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Format: Article
Language:en_US
Published: Institute of Electrical and Electronics Engineers (IEEE) 2015
Online Access:http://hdl.handle.net/1721.1/96843
https://orcid.org/0000-0001-8253-7714
https://orcid.org/0000-0003-3437-7570
https://orcid.org/0000-0002-7044-5684
https://orcid.org/0000-0003-1467-2150

Internet

http://hdl.handle.net/1721.1/96843
https://orcid.org/0000-0001-8253-7714
https://orcid.org/0000-0003-3437-7570
https://orcid.org/0000-0002-7044-5684
https://orcid.org/0000-0003-1467-2150

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