An arbitration state controller for a Digital Equipment Corporation computer bus
Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 1981.
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | eng |
| Published: |
Massachusetts Institute of Technology
2005
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/1721.1/9723 |
| _version_ | 1826214077850976256 |
|---|---|
| author | Mandry, James Edward |
| author2 | Jonathan Allen. |
| author_facet | Jonathan Allen. Mandry, James Edward |
| author_sort | Mandry, James Edward |
| collection | MIT |
| description | Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 1981. |
| first_indexed | 2024-09-23T15:59:27Z |
| format | Thesis |
| id | mit-1721.1/9723 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T15:59:27Z |
| publishDate | 2005 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/97232020-07-14T22:02:08Z An arbitration state controller for a Digital Equipment Corporation computer bus Mandry, James Edward Jonathan Allen. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Electrical Engineering and Computer Science Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 1981. "May, 1981." This thesis will outline the work performed in designing an Arbitration State Controller for a bus conforming to the specifications of Digital Equipment Corporation (DEC) as noted briefly below and as further noted in a DEC specification document. The bus is used to join a processor to integral I/0 controllers, I/0 bus adapters, memories, or other processors. Its characteristics are low cost, short length, high bandwidth, a moderate number of drops, a large addressing range, and data integrity. Arbitration logic is distributed among all devices capable of becoming bus masters (i.e., senders of command/address information). Bus arbitration occurs over a single bus cycle. A device arbitrates for the bus by asserting one of the data lines during an arbitration cycle. During the second half of the cycle, the device determines if there were any lower number data lines asserted during the arbitration cycle and if not, then that device wins the bus and may send command/address information when the current bus transaction (if one exists) has completed. Arbitration cycles occur during idle bus cycles or during an imbedded arbitration cycle in a bus transaction and are indicated by the use of the NO ARB signal. The data lines are reserved for arbitration information on the cycle following one which has NO ARB unasserted. An initial design utilizing an encoder, a comparator, a decoder, and random logic has been designed and must be further tested. by James Edward Mandry. B.S. 2005-08-19T19:43:43Z 2005-08-19T19:43:43Z 1981 Thesis http://hdl.handle.net/1721.1/9723 42679737 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 63 leaves 4281813 bytes 4281570 bytes application/pdf application/pdf application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science Mandry, James Edward An arbitration state controller for a Digital Equipment Corporation computer bus |
| title | An arbitration state controller for a Digital Equipment Corporation computer bus |
| title_full | An arbitration state controller for a Digital Equipment Corporation computer bus |
| title_fullStr | An arbitration state controller for a Digital Equipment Corporation computer bus |
| title_full_unstemmed | An arbitration state controller for a Digital Equipment Corporation computer bus |
| title_short | An arbitration state controller for a Digital Equipment Corporation computer bus |
| title_sort | arbitration state controller for a digital equipment corporation computer bus |
| topic | Electrical Engineering and Computer Science |
| url | http://hdl.handle.net/1721.1/9723 |
| work_keys_str_mv | AT mandryjamesedward anarbitrationstatecontrollerforadigitalequipmentcorporationcomputerbus AT mandryjamesedward arbitrationstatecontrollerforadigitalequipmentcorporationcomputerbus |