Reducing data movement in multicore chips with computation and data co-scheduling
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
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| Format: | Thesis |
| Language: | eng |
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Massachusetts Institute of Technology
2015
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| Online Access: | http://hdl.handle.net/1721.1/99839 |
| _version_ | 1826190295085088768 |
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| author | Tsai, Po-An |
| author2 | Daniel Sanchez. |
| author_facet | Daniel Sanchez. Tsai, Po-An |
| author_sort | Tsai, Po-An |
| collection | MIT |
| description | Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015. |
| first_indexed | 2024-09-23T08:38:04Z |
| format | Thesis |
| id | mit-1721.1/99839 |
| institution | Massachusetts Institute of Technology |
| language | eng |
| last_indexed | 2024-09-23T08:38:04Z |
| publishDate | 2015 |
| publisher | Massachusetts Institute of Technology |
| record_format | dspace |
| spelling | mit-1721.1/998392019-04-09T18:52:42Z Reducing data movement in multicore chips with computation and data co-scheduling Tsai, Po-An Daniel Sanchez. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Electrical Engineering and Computer Science. Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015. Cataloged from PDF version of thesis. Includes bibliographical references (pages 59-63). Energy efficiency is the main limitation to the performance of parallel systems. Current architectures often focus on making cores more efficient. However, data movement is much more costly than basic compute operations. For example, at 28 nm, a main memory access is 100x slower and consumes 1000x the energy of a floatingpoint operation, and moving 64 bytes across a 16-core processor is 50 x slower and consumes 20 x the energy. Without a drastic reduction in data movement, memory accesses and communication costs will limit the scalability of future computing systems. Conventional hardware-only and software-only techniques miss many opportunities to reduce data movement. This thesis presents computation and data co-scheduling (CDCS), a technique that jointly performs computation and data placement to reduce both on-chip and off-chip data movement. CDCS integrates hardware and software techniques: Hardware lets software control data mapping to physically distributed caches, and software uses this support to periodically reconfigure the chip, minimizing data movement. On a simulated 64-core system, CDCS outperforms a standard last-level cache by 46% on average (up to 76%) in weighted speedup, reduces both on-chip network traffic (by 11 x) and off-chip traffic (by 23%), and saves 36% of system energy. by Po-An Tsai. S.M. 2015-11-09T19:52:18Z 2015-11-09T19:52:18Z 2015 2015 Thesis http://hdl.handle.net/1721.1/99839 927408726 eng M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 63 pages application/pdf Massachusetts Institute of Technology |
| spellingShingle | Electrical Engineering and Computer Science. Tsai, Po-An Reducing data movement in multicore chips with computation and data co-scheduling |
| title | Reducing data movement in multicore chips with computation and data co-scheduling |
| title_full | Reducing data movement in multicore chips with computation and data co-scheduling |
| title_fullStr | Reducing data movement in multicore chips with computation and data co-scheduling |
| title_full_unstemmed | Reducing data movement in multicore chips with computation and data co-scheduling |
| title_short | Reducing data movement in multicore chips with computation and data co-scheduling |
| title_sort | reducing data movement in multicore chips with computation and data co scheduling |
| topic | Electrical Engineering and Computer Science. |
| url | http://hdl.handle.net/1721.1/99839 |
| work_keys_str_mv | AT tsaipoan reducingdatamovementinmulticorechipswithcomputationanddatacoscheduling |