III–V compound semiconductor transistors—from planar to nanowire structures
Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III–V compound semiconductors that are well...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | en_US |
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Cambridge University Press (Materials Research Society)
2015
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| Online Access: | http://hdl.handle.net/1721.1/99977 |
| _version_ | 1811091350107455488 |
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| author | Riel, Heike Wernersson, Lars-Erik Hong, Minghwei del Alamo, Jesus A. |
| author2 | Massachusetts Institute of Technology. Microsystems Technology Laboratories |
| author_facet | Massachusetts Institute of Technology. Microsystems Technology Laboratories Riel, Heike Wernersson, Lars-Erik Hong, Minghwei del Alamo, Jesus A. |
| author_sort | Riel, Heike |
| collection | MIT |
| description | Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III–V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III–V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III–V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III–V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS applications. |
| first_indexed | 2024-09-23T15:01:05Z |
| format | Article |
| id | mit-1721.1/99977 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T15:01:05Z |
| publishDate | 2015 |
| publisher | Cambridge University Press (Materials Research Society) |
| record_format | dspace |
| spelling | mit-1721.1/999772022-10-01T23:59:11Z III–V compound semiconductor transistors—from planar to nanowire structures Riel, Heike Wernersson, Lars-Erik Hong, Minghwei del Alamo, Jesus A. Massachusetts Institute of Technology. Microsystems Technology Laboratories del Alamo, Jesus A. Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III–V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III–V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III–V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III–V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS applications. Focus Center Research Program. Center for Materials, Structures and Devices Intel Corporation United States. Army Research Laboratory Semiconductor Research Corporation National Science Foundation (U.S.) (Award 0939514) Sematech 2015-11-23T13:22:50Z 2015-11-23T13:22:50Z 2014-08 Article http://purl.org/eprint/type/JournalArticle 0883-7694 1938-1425 http://hdl.handle.net/1721.1/99977 Riel, Heike, Lars-Erik Wernersson, Minghwei Hong, and Jesus A. del Alamo. “III–V Compound Semiconductor Transistors—from Planar to Nanowire Structures.” MRS Bulletin 39, no. 08 (August 2014): 668–677. © 2014 Materials Research Society en_US http://dx.doi.org/10.1557/mrs.2014.137 MRS Bulletin Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. application/pdf Cambridge University Press (Materials Research Society) MIT web domain |
| spellingShingle | Riel, Heike Wernersson, Lars-Erik Hong, Minghwei del Alamo, Jesus A. III–V compound semiconductor transistors—from planar to nanowire structures |
| title | III–V compound semiconductor transistors—from planar to nanowire structures |
| title_full | III–V compound semiconductor transistors—from planar to nanowire structures |
| title_fullStr | III–V compound semiconductor transistors—from planar to nanowire structures |
| title_full_unstemmed | III–V compound semiconductor transistors—from planar to nanowire structures |
| title_short | III–V compound semiconductor transistors—from planar to nanowire structures |
| title_sort | iii v compound semiconductor transistors from planar to nanowire structures |
| url | http://hdl.handle.net/1721.1/99977 |
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