Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs
Oblivious RAM (ORAM) is an established cryptographic technique to hide a program's address pattern to an untrusted storage system. More recently, ORAM schemes have been proposed to replace conventional memory controllers in secure processor settings to protect against information leakage in ext...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | en_US |
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Institute of Electrical and Electronics Engineers (IEEE)
2015
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| Online Access: | http://hdl.handle.net/1721.1/99988 https://orcid.org/0000-0001-8253-7714 https://orcid.org/0000-0003-3437-7570 https://orcid.org/0000-0003-4317-3457 https://orcid.org/0000-0003-1467-2150 |
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| author | Ren, Ling Yu, Xiangyao Van Dijk, Marten Khan, Omer Devadas, Srinivas Fletcher, Christopher Wardlaw |
| author2 | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science |
| author_facet | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Ren, Ling Yu, Xiangyao Van Dijk, Marten Khan, Omer Devadas, Srinivas Fletcher, Christopher Wardlaw |
| author_sort | Ren, Ling |
| collection | MIT |
| description | Oblivious RAM (ORAM) is an established cryptographic technique to hide a program's address pattern to an untrusted storage system. More recently, ORAM schemes have been proposed to replace conventional memory controllers in secure processor settings to protect against information leakage in external memory and the processor I/O bus. A serious problem in current secure processor ORAM proposals is that they don't obfuscate when ORAM accesses are made, or do so in a very conservative manner. Since secure processors make ORAM accesses on last-level cache misses, ORAM access timing strongly correlates to program access pattern (e.g., locality). This brings ORAM's purpose in secure processors into question. This paper makes two contributions. First, we show how a secure processor can bound ORAM timing channel leakage to a user-controllable leakage limit. The secure processor is allowed to dynamically optimize ORAM access rate for power/performance, subject to the constraint that the leakage limit is not violated. Second, we show how changing the leakage limit impacts program efficiency. We present a dynamic scheme that leaks at most 32 bits through the ORAM timing channel and introduces only 20% performance overhead and 12% power overhead relative to a baseline ORAM that has no timing channel protection. By reducing leakage to 16 bits, our scheme degrades in performance by 5% but gains in power efficiency by 3%. We show that a static (zero leakage) scheme imposes a 34% power overhead for equivalent performance (or a 30% performance overhead for equivalent power) relative to our dynamic scheme. |
| first_indexed | 2024-09-23T08:58:27Z |
| format | Article |
| id | mit-1721.1/99988 |
| institution | Massachusetts Institute of Technology |
| language | en_US |
| last_indexed | 2024-09-23T08:58:27Z |
| publishDate | 2015 |
| publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| record_format | dspace |
| spelling | mit-1721.1/999882022-09-26T09:33:20Z Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs Ren, Ling Yu, Xiangyao Van Dijk, Marten Khan, Omer Devadas, Srinivas Fletcher, Christopher Wardlaw Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Fletcher, Christopher Wardlaw Ren, Ling Yu, Xiangyao Devadas, Srinivas Oblivious RAM (ORAM) is an established cryptographic technique to hide a program's address pattern to an untrusted storage system. More recently, ORAM schemes have been proposed to replace conventional memory controllers in secure processor settings to protect against information leakage in external memory and the processor I/O bus. A serious problem in current secure processor ORAM proposals is that they don't obfuscate when ORAM accesses are made, or do so in a very conservative manner. Since secure processors make ORAM accesses on last-level cache misses, ORAM access timing strongly correlates to program access pattern (e.g., locality). This brings ORAM's purpose in secure processors into question. This paper makes two contributions. First, we show how a secure processor can bound ORAM timing channel leakage to a user-controllable leakage limit. The secure processor is allowed to dynamically optimize ORAM access rate for power/performance, subject to the constraint that the leakage limit is not violated. Second, we show how changing the leakage limit impacts program efficiency. We present a dynamic scheme that leaks at most 32 bits through the ORAM timing channel and introduces only 20% performance overhead and 12% power overhead relative to a baseline ORAM that has no timing channel protection. By reducing leakage to 16 bits, our scheme degrades in performance by 5% but gains in power efficiency by 3%. We show that a static (zero leakage) scheme imposes a 34% power overhead for equivalent performance (or a 30% performance overhead for equivalent power) relative to our dynamic scheme. United States. Dept. of Defense (National Defense Science and Engineering Graduate (NDSEG) Fellowship) United States. Defense Advanced Research Projects Agency. Clean-slate Design of Resilient, Adaptive, Secure Hosts (CRASH) Program (Contract N66001-10-2-4089) 2015-11-23T15:09:04Z 2015-11-23T15:09:04Z 2014-02 Article http://purl.org/eprint/type/ConferencePaper 978-1-4799-3097-5 http://hdl.handle.net/1721.1/99988 Fletcher, Christopher W., Ling Ren, Xiangyao Yu, Marten Van Dijk, Omer Khan, and Srinivas Devadas. “Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-Offs.” 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) (February 2014). https://orcid.org/0000-0001-8253-7714 https://orcid.org/0000-0003-3437-7570 https://orcid.org/0000-0003-4317-3457 https://orcid.org/0000-0003-1467-2150 en_US http://dx.doi.org/10.1109/HPCA.2014.6835932 Proceedings of the 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) Creative Commons Attribution-Noncommercial-Share Alike http://creativecommons.org/licenses/by-nc-sa/4.0/ application/pdf Institute of Electrical and Electronics Engineers (IEEE) MIT web domain |
| spellingShingle | Ren, Ling Yu, Xiangyao Van Dijk, Marten Khan, Omer Devadas, Srinivas Fletcher, Christopher Wardlaw Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs |
| title | Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs |
| title_full | Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs |
| title_fullStr | Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs |
| title_full_unstemmed | Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs |
| title_short | Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs |
| title_sort | suppressing the oblivious ram timing channel while making information leakage and program efficiency trade offs |
| url | http://hdl.handle.net/1721.1/99988 https://orcid.org/0000-0001-8253-7714 https://orcid.org/0000-0003-3437-7570 https://orcid.org/0000-0003-4317-3457 https://orcid.org/0000-0003-1467-2150 |
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