0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique
A dual-modulus prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phase-locked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a wide-range operating, signif...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/102377 http://hdl.handle.net/10220/16515 |
| _version_ | 1826127098377404416 |
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| author | Yu, Xiao Peng Lu, Zhenghao Lim, Wei Meng Yeo, Kiat Seng |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Yu, Xiao Peng Lu, Zhenghao Lim, Wei Meng Yeo, Kiat Seng |
| author_sort | Yu, Xiao Peng |
| collection | NTU |
| description | A dual-modulus prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phase-locked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a wide-range operating, significantly reduced settling time and low power consumption are achieved. Implemented in a standard 40nm CMOS process, the proposed divide-by-2 and 3 dual-modulus prescaler achieves an operating frequency of 6.3GHz with a measured power consumption of 0.6mW from a 1.1V supply. |
| first_indexed | 2024-10-01T07:03:11Z |
| format | Journal Article |
| id | ntu-10356/102377 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:03:11Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/1023772020-03-07T14:00:33Z 0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique Yu, Xiao Peng Lu, Zhenghao Lim, Wei Meng Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering A dual-modulus prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phase-locked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a wide-range operating, significantly reduced settling time and low power consumption are achieved. Implemented in a standard 40nm CMOS process, the proposed divide-by-2 and 3 dual-modulus prescaler achieves an operating frequency of 6.3GHz with a measured power consumption of 0.6mW from a 1.1V supply. 2013-10-16T04:19:06Z 2019-12-06T20:54:06Z 2013-10-16T04:19:06Z 2019-12-06T20:54:06Z 2013 2013 Journal Article Yu, X. P., Lu, Z.H., Lim, W.M., & Yeo, K.S. (2013). 0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique. Electronics letters, 49(7), 471-472. 0013-5194 https://hdl.handle.net/10356/102377 http://hdl.handle.net/10220/16515 10.1049/el.2013.0584 en Electronics Letters © 2013 The Institution of Engineering and Technology. |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Yu, Xiao Peng Lu, Zhenghao Lim, Wei Meng Yeo, Kiat Seng 0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique |
| title | 0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique |
| title_full | 0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique |
| title_fullStr | 0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique |
| title_full_unstemmed | 0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique |
| title_short | 0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique |
| title_sort | 0 6mw 6 3 ghz 40nm cmos divide by 2 3 prescaler using heterodyne phase locking technique |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/102377 http://hdl.handle.net/10220/16515 |
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