Synchronous-logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors
We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power...
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| Format: | Journal Article |
| Language: | English |
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2013
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| Online Access: | https://hdl.handle.net/10356/102558 http://hdl.handle.net/10220/16395 |
| _version_ | 1826122110820417536 |
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| author | Chong, Kwen-Siong Chang, Kok-Leong Gwee, Bah Hwee Chang, Joseph Sylvester |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Chong, Kwen-Siong Chang, Kok-Leong Gwee, Bah Hwee Chang, Joseph Sylvester |
| author_sort | Chong, Kwen-Siong |
| collection | NTU |
| description | We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal VDD = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery (VDD = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at VDD = 1.2 V, it dissipates 186 μW. |
| first_indexed | 2024-10-01T05:43:08Z |
| format | Journal Article |
| id | ntu-10356/102558 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:43:08Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/1025582020-03-07T12:47:21Z Synchronous-logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors Chong, Kwen-Siong Chang, Kok-Leong Gwee, Bah Hwee Chang, Joseph Sylvester School of Electrical and Electronic Engineering Temasek Laboratories DRNTU::Engineering::Electrical and electronic engineering We design an Acoustic Digital Signal Processor (ADSP) SoC, the primary signal processing module of an acoustic signal detection system, based on two design approaches: fully-synchronous (Fully-Sync), and globally-asynchronous-locally-synchronous (GALS). The emphasis of the ADSP designs is low power operation where both designs embody modular-level and circuit-level clock gating techniques. For sake of fair benchmarking, both ADSPs have identical functionality, are designed using the same 130 nm CMOS process, and largely embody the same library cells (save that for the signaling protocols in the GALS ADSP). The GALS ADSP is substantially more power-efficient (the Fully-Sync ADSP dissipates 1.9× more power @ nominal VDD = 1.2 V) and the only cost is the marginally higher (1.02×) IC area. Its higher power efficiency is largely attributed to the exploitation of asynchronous signaling between circuit modules by means of more finely-grained partitioning of the clock domains; intra-circuit signaling therein remains fully-sync. This provides for the ensuing simplification of the clocking infrastructure and subsequent reduction of the global clock rate. The prototype GALS ADSP is able to operate to specifications throughout the lifespan of the battery (VDD = 0.9 V-1.4 V, in part depicting Dynamic Voltage Scaling attributes) and at VDD = 1.2 V, it dissipates 186 μW. 2013-10-10T06:20:13Z 2019-12-06T20:56:55Z 2013-10-10T06:20:13Z 2019-12-06T20:56:55Z 2012 2012 Journal Article Chong, K. S., Chang, K. L., Gwee, B. H., & Chang, J. S. (2012). Synchronous-logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors. IEEE journal of solid-state circuits, 47(3), 769-780. https://hdl.handle.net/10356/102558 http://hdl.handle.net/10220/16395 10.1109/JSSC.2011.2181678 en IEEE journal of solid-state circuits |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Chong, Kwen-Siong Chang, Kok-Leong Gwee, Bah Hwee Chang, Joseph Sylvester Synchronous-logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors |
| title | Synchronous-logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors |
| title_full | Synchronous-logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors |
| title_fullStr | Synchronous-logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors |
| title_full_unstemmed | Synchronous-logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors |
| title_short | Synchronous-logic and globally-asynchronous-locally-synchronous (GALS) acoustic digital signal processors |
| title_sort | synchronous logic and globally asynchronous locally synchronous gals acoustic digital signal processors |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/102558 http://hdl.handle.net/10220/16395 |
| work_keys_str_mv | AT chongkwensiong synchronouslogicandgloballyasynchronouslocallysynchronousgalsacousticdigitalsignalprocessors AT changkokleong synchronouslogicandgloballyasynchronouslocallysynchronousgalsacousticdigitalsignalprocessors AT gweebahhwee synchronouslogicandgloballyasynchronouslocallysynchronousgalsacousticdigitalsignalprocessors AT changjosephsylvester synchronouslogicandgloballyasynchronouslocallysynchronousgalsacousticdigitalsignalprocessors |