Obfuscation and watermarking of FPGA designs based on constant value generators
Obfuscation is a technique which makes design less intelligible in order to prevent or increase reverse engineering effort. In this paper, a new approach to hardware obfuscation by inserting constant value generators (CVGs) is proposed. A CVG is a circuit that generates the same fixed logic value bu...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2015
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| Online Access: | https://hdl.handle.net/10356/105039 http://hdl.handle.net/10220/25168 http://dx.doi.org/10.1109/ISICIR.2014.7029471 |
| _version_ | 1811679945785606144 |
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| author | Sergeichik, Vladimir V. Ivaniuk, Alexander A. Chang, Chip-Hong |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Sergeichik, Vladimir V. Ivaniuk, Alexander A. Chang, Chip-Hong |
| author_sort | Sergeichik, Vladimir V. |
| collection | NTU |
| description | Obfuscation is a technique which makes design less intelligible in order to prevent or increase reverse engineering effort. In this paper, a new approach to hardware obfuscation by inserting constant value generators (CVGs) is proposed. A CVG is a circuit that generates the same fixed logic value but will not be minimized by the synthesizer. CVGs can be used to create new logic primitives, embed watermarks and introduce fictive interdependencies in the circuit. They help to hide actual design performance information by tricking the synthesizer tools to generate deceiving delay reports through the false paths. |
| first_indexed | 2024-10-01T03:17:13Z |
| format | Conference Paper |
| id | ntu-10356/105039 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:17:13Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/1050392019-12-06T21:44:55Z Obfuscation and watermarking of FPGA designs based on constant value generators Sergeichik, Vladimir V. Ivaniuk, Alexander A. Chang, Chip-Hong School of Electrical and Electronic Engineering International Symposium on Integrated Circuits (ISIC) (14th : 2014) DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Obfuscation is a technique which makes design less intelligible in order to prevent or increase reverse engineering effort. In this paper, a new approach to hardware obfuscation by inserting constant value generators (CVGs) is proposed. A CVG is a circuit that generates the same fixed logic value but will not be minimized by the synthesizer. CVGs can be used to create new logic primitives, embed watermarks and introduce fictive interdependencies in the circuit. They help to hide actual design performance information by tricking the synthesizer tools to generate deceiving delay reports through the false paths. Accepted version 2015-03-03T09:21:08Z 2019-12-06T21:44:55Z 2015-03-03T09:21:08Z 2019-12-06T21:44:55Z 2014 2014 Conference Paper Sergeichik, V. V., Ivaniuk, A. A., & Chang, C.-H. (2014). Obfuscation and watermarking of FPGA designs based on constant value generators. 2014 14th International Symposium on Integrated Circuits (ISIC), 608-611. https://hdl.handle.net/10356/105039 http://hdl.handle.net/10220/25168 http://dx.doi.org/10.1109/ISICIR.2014.7029471 183019 en © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISICIR.2014.7029471]. 4 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Sergeichik, Vladimir V. Ivaniuk, Alexander A. Chang, Chip-Hong Obfuscation and watermarking of FPGA designs based on constant value generators |
| title | Obfuscation and watermarking of FPGA designs based on constant value generators |
| title_full | Obfuscation and watermarking of FPGA designs based on constant value generators |
| title_fullStr | Obfuscation and watermarking of FPGA designs based on constant value generators |
| title_full_unstemmed | Obfuscation and watermarking of FPGA designs based on constant value generators |
| title_short | Obfuscation and watermarking of FPGA designs based on constant value generators |
| title_sort | obfuscation and watermarking of fpga designs based on constant value generators |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | https://hdl.handle.net/10356/105039 http://hdl.handle.net/10220/25168 http://dx.doi.org/10.1109/ISICIR.2014.7029471 |
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