A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS
Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage i...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2013
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| Online Access: | https://hdl.handle.net/10356/105327 http://hdl.handle.net/10220/16578 http://dx.doi.org/10.1109/ISSCC.2013.6487739 |
| _version_ | 1811685106412158976 |
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| author | Han, Dong Zheng, Yuanjin Rajkumar, Ramamoorthy Dawe, Gavin Je, Minkyu |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Han, Dong Zheng, Yuanjin Rajkumar, Ramamoorthy Dawe, Gavin Je, Minkyu |
| author_sort | Han, Dong |
| collection | NTU |
| description | Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction. |
| first_indexed | 2024-10-01T04:39:15Z |
| format | Conference Paper |
| id | ntu-10356/105327 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:39:15Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/1053272019-12-06T21:49:15Z A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS Han, Dong Zheng, Yuanjin Rajkumar, Ramamoorthy Dawe, Gavin Je, Minkyu School of Electrical and Electronic Engineering IEEE International Solid-State Circuits Conference (2013 : San Francisco, California, US) DRNTU::Engineering::Electrical and electronic engineering Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction. 2013-10-18T02:35:18Z 2019-12-06T21:49:15Z 2013-10-18T02:35:18Z 2019-12-06T21:49:15Z 2013 2013 Conference Paper Han, D., Zheng, Y., Rajkumar, R., Dawe, G., & Je, M. (2013). A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 290 - 291. https://hdl.handle.net/10356/105327 http://hdl.handle.net/10220/16578 http://dx.doi.org/10.1109/ISSCC.2013.6487739 en |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Han, Dong Zheng, Yuanjin Rajkumar, Ramamoorthy Dawe, Gavin Je, Minkyu A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS |
| title | A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS |
| title_full | A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS |
| title_fullStr | A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS |
| title_full_unstemmed | A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS |
| title_short | A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS |
| title_sort | 0 45v 100 channel neural recording ic with sub µw channel consumption in 0 18µm cmos |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/105327 http://hdl.handle.net/10220/16578 http://dx.doi.org/10.1109/ISSCC.2013.6487739 |
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