0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance

0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance

This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the dela...

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Podrobná bibliografie
Hlavní autoři: Do, Anh Tuan, Yin, Chun, Velayudhan, Kavitha, Lee, Zhao Chuan, Yeo, Kiat Seng, Kim, Tony Tae-Hyoung
Další autoři: School of Electrical and Electronic Engineering
Médium: Journal Article
Jazyk:English
Vydáno: 2014
Témata:
DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
On-line přístup:https://hdl.handle.net/10356/105356
http://hdl.handle.net/10220/20473
http://dx.doi.org/10.1109/JSSC.2014.2316241

Internet

https://hdl.handle.net/10356/105356
http://hdl.handle.net/10220/20473
http://dx.doi.org/10.1109/JSSC.2014.2316241

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