Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of area-power efficient fir filters
Finite impulse response filters are widely used in digital signal processing applications. Prodigious research in the past two decades has substantially reduced the implementation cost of the multiple constant multiplication block. Further area and power consumption savings are stagnated by the stru...
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| Format: | Journal Article |
| Language: | English |
| Published: |
2019
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| Online Access: | https://hdl.handle.net/10356/105545 http://hdl.handle.net/10220/47824 http://dx.doi.org/10.1109/TCSI.2017.2725916 |
| _version_ | 1826118638491402240 |
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| author | Qiao, Rui Faust, Mathias Chen, Jiajia Chang, Chip-Hong Ding, Jiatao |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Qiao, Rui Faust, Mathias Chen, Jiajia Chang, Chip-Hong Ding, Jiatao |
| author_sort | Qiao, Rui |
| collection | NTU |
| description | Finite impulse response filters are widely used in digital signal processing applications. Prodigious research in the past two decades has substantially reduced the implementation cost of the multiple constant multiplication block. Further area and power consumption savings are stagnated by the structural adders and registers in the tap delay-and-accumulate line, which unfortunately dominate the overall hardware cost of FIR filter and are difficult to minimize by existing resource sharing approaches. Retiming or relocating the structural adders and registers can improve merely the throughput. To close the area-power efficiency gap, we reformulate the filter coefficient synthesis problem to explore the design space for the tap delay-and accumulate line by bisecting at some tap position. An efficient Genetic Algorithm is proposed to solve this integer programming problem at quadratic computational complexity by refining the search space for finding an optimized solution to fulfill the frequency response specifications. FPGA and ASIC logic synthesis results from twelve benchmark filter specifications showed that the average area and power consumptions of the solutions generated by our proposed algorithm have been reduced by up to 26.8% and 27.5% respectively, in comparison with the solutions obtained by existing design methods. |
| first_indexed | 2024-10-01T04:46:45Z |
| format | Journal Article |
| id | ntu-10356/105545 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:46:45Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/1055452019-12-06T21:53:18Z Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of area-power efficient fir filters Qiao, Rui Faust, Mathias Chen, Jiajia Chang, Chip-Hong Ding, Jiatao School of Electrical and Electronic Engineering Structural Adder FIR Filter Design DRNTU::Engineering::Electrical and electronic engineering Finite impulse response filters are widely used in digital signal processing applications. Prodigious research in the past two decades has substantially reduced the implementation cost of the multiple constant multiplication block. Further area and power consumption savings are stagnated by the structural adders and registers in the tap delay-and-accumulate line, which unfortunately dominate the overall hardware cost of FIR filter and are difficult to minimize by existing resource sharing approaches. Retiming or relocating the structural adders and registers can improve merely the throughput. To close the area-power efficiency gap, we reformulate the filter coefficient synthesis problem to explore the design space for the tap delay-and accumulate line by bisecting at some tap position. An efficient Genetic Algorithm is proposed to solve this integer programming problem at quadratic computational complexity by refining the search space for finding an optimized solution to fulfill the frequency response specifications. FPGA and ASIC logic synthesis results from twelve benchmark filter specifications showed that the average area and power consumptions of the solutions generated by our proposed algorithm have been reduced by up to 26.8% and 27.5% respectively, in comparison with the solutions obtained by existing design methods. Accepted version 2019-03-15T06:41:56Z 2019-12-06T21:53:17Z 2019-03-15T06:41:56Z 2019-12-06T21:53:17Z 2018 Journal Article Chen, J., Chang, C.-H., Ding, J., Qiao, R., & Faust, M. (2018). Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of area-power efficient fir filters. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(2), 712-722. doi:10.1109/TCSI.2017.2725916 1549-8328 https://hdl.handle.net/10356/105545 http://hdl.handle.net/10220/47824 http://dx.doi.org/10.1109/TCSI.2017.2725916 en IEEE Transactions on Circuits and Systems I: Regular Papers © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TCSI.2017.2725916 11 p. application/pdf |
| spellingShingle | Structural Adder FIR Filter Design DRNTU::Engineering::Electrical and electronic engineering Qiao, Rui Faust, Mathias Chen, Jiajia Chang, Chip-Hong Ding, Jiatao Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of area-power efficient fir filters |
| title | Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of area-power efficient fir filters |
| title_full | Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of area-power efficient fir filters |
| title_fullStr | Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of area-power efficient fir filters |
| title_full_unstemmed | Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of area-power efficient fir filters |
| title_short | Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of area-power efficient fir filters |
| title_sort | tap delay and accumulate cost aware coefficient synthesis algorithm for the design of area power efficient fir filters |
| topic | Structural Adder FIR Filter Design DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/105545 http://hdl.handle.net/10220/47824 http://dx.doi.org/10.1109/TCSI.2017.2725916 |
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