New hardware and power efficient sporadic logarithmic shifters for DSP applications
Shifting an input data by variable amounts is commonly found in arithmetic operations, data encoding and bit-indexing. Although some shift amounts along the entire shift range are not required, the typical realization by a full-range logarithm shifter requires full implementation and therefore suff...
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2019
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| Online Access: | https://hdl.handle.net/10356/105840 http://hdl.handle.net/10220/47854 http://dx.doi.org/10.1109/TCAD.2017.2740300 |
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| author | Chen, Jiajia Chang, Chip-Hong Wang, Yujia Zhao, Juan Rahardja, Susanto |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Chen, Jiajia Chang, Chip-Hong Wang, Yujia Zhao, Juan Rahardja, Susanto |
| author_sort | Chen, Jiajia |
| collection | NTU |
| description | Shifting an input data by variable amounts is commonly found in arithmetic operations, data encoding and bit-indexing. Although some shift amounts along the entire shift range are not required, the typical realization by a full-range
logarithm shifter requires full implementation and therefore suffers from complexity and power overhead. In this paper, the notion of sporadic logarithmic shifter is introduced for the first time, and a new design methodology is proposed for its
optimization. By reusing parts of existing substructure of conventional logarithmic shifter or post-multiplexing the
hardwired shifts, contagious subranges of desirable shift amounts are successively realized. Synthesis results on 8-bit and
16-bit sporadic logarithmic shifters show average ASIC area and power savings of up to 73.24% and 63.90% respectively, over conventional logarithmic shifters. In addition, by applying the proposed sporadic logarithmic shifters to the DCT architecture, at least 47.5% area savings and 2.9% power savings can be achieved over two constant multipliers based DCT architectures reported in the literature. |
| first_indexed | 2024-10-01T02:48:23Z |
| format | Journal Article |
| id | ntu-10356/105840 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:48:23Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/1058402019-12-06T21:59:05Z New hardware and power efficient sporadic logarithmic shifters for DSP applications Chen, Jiajia Chang, Chip-Hong Wang, Yujia Zhao, Juan Rahardja, Susanto School of Electrical and Electronic Engineering Digital IC Design Digital Signal Processing DRNTU::Engineering::Electrical and electronic engineering Shifting an input data by variable amounts is commonly found in arithmetic operations, data encoding and bit-indexing. Although some shift amounts along the entire shift range are not required, the typical realization by a full-range logarithm shifter requires full implementation and therefore suffers from complexity and power overhead. In this paper, the notion of sporadic logarithmic shifter is introduced for the first time, and a new design methodology is proposed for its optimization. By reusing parts of existing substructure of conventional logarithmic shifter or post-multiplexing the hardwired shifts, contagious subranges of desirable shift amounts are successively realized. Synthesis results on 8-bit and 16-bit sporadic logarithmic shifters show average ASIC area and power savings of up to 73.24% and 63.90% respectively, over conventional logarithmic shifters. In addition, by applying the proposed sporadic logarithmic shifters to the DCT architecture, at least 47.5% area savings and 2.9% power savings can be achieved over two constant multipliers based DCT architectures reported in the literature. Accepted version 2019-03-19T05:10:10Z 2019-12-06T21:59:05Z 2019-03-19T05:10:10Z 2019-12-06T21:59:05Z 2017 Journal Article Chen, J., Chang, C.-H., Wang, Y., Zhao, J., & Rahardja, S. (2018). New hardware and power efficient sporadic logarithmic shifters for DSP applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(4), 896-900. doi:10.1109/TCAD.2017.2740300 0278-0070 https://hdl.handle.net/10356/105840 http://hdl.handle.net/10220/47854 http://dx.doi.org/10.1109/TCAD.2017.2740300 en IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TCAD.2017.2740300 5 p. application/pdf |
| spellingShingle | Digital IC Design Digital Signal Processing DRNTU::Engineering::Electrical and electronic engineering Chen, Jiajia Chang, Chip-Hong Wang, Yujia Zhao, Juan Rahardja, Susanto New hardware and power efficient sporadic logarithmic shifters for DSP applications |
| title | New hardware and power efficient sporadic logarithmic shifters for DSP applications |
| title_full | New hardware and power efficient sporadic logarithmic shifters for DSP applications |
| title_fullStr | New hardware and power efficient sporadic logarithmic shifters for DSP applications |
| title_full_unstemmed | New hardware and power efficient sporadic logarithmic shifters for DSP applications |
| title_short | New hardware and power efficient sporadic logarithmic shifters for DSP applications |
| title_sort | new hardware and power efficient sporadic logarithmic shifters for dsp applications |
| topic | Digital IC Design Digital Signal Processing DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/105840 http://hdl.handle.net/10220/47854 http://dx.doi.org/10.1109/TCAD.2017.2740300 |
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