An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability
We propose a dynamic voltage scalable SRAM capable of efficient bit-interleaving in column to tolerate multiple-bits soft error when integrated with error correction codes (ECC). First, a 10T SRAM bitcell is proposed. It activates only intended bitcells so that stability problem of half-selected bit...
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
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2013
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| Online Access: | https://hdl.handle.net/10356/106455 http://hdl.handle.net/10220/17694 http://dx.doi.org/10.1109/ISCAS.2012.6271625 |
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| author | Chen, Junchao Chong, Kwen-Siong Gwee, Bah Hwee Chang, Joseph Sylvester |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Chen, Junchao Chong, Kwen-Siong Gwee, Bah Hwee Chang, Joseph Sylvester |
| author_sort | Chen, Junchao |
| collection | NTU |
| description | We propose a dynamic voltage scalable SRAM capable of efficient bit-interleaving in column to tolerate multiple-bits soft error when integrated with error correction codes (ECC). First, a 10T SRAM bitcell is proposed. It activates only intended bitcells so that stability problem of half-selected bitcells is completely eliminated and the power dissipation in half-selected columns is significantly reduced. Second, a configurable DVS scheme is employed to enable the bitcell to operate like differential 8T during super-threshold region which results in faster operation. The proposed SRAM can operate up to 1.2GHz at 1.2V using 65nm CMOS process. Third, a segmented column multiplex with low overhead is proposed, which greatly reduces the power dissipation due to the column control signals. Consequently, the write and read power dissipations are reduced by up to 40% and 67% respectively. Forth, a hierarchical read bitline is used to reduce the read bitline discharge delay variation due to local and global process variation in subthreshold region, which is a major portion of memory access time. Based on our simulation results, the worst case read bitline discharge delay is reduced by more than 12× at VDD of 0.3V. |
| first_indexed | 2024-10-01T02:55:12Z |
| format | Conference Paper |
| id | ntu-10356/106455 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:55:12Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/1064552019-12-06T22:12:09Z An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability Chen, Junchao Chong, Kwen-Siong Gwee, Bah Hwee Chang, Joseph Sylvester School of Electrical and Electronic Engineering IEEE International Symposium on Circuits and Systems (2012 : Seoul, Korea) DRNTU::Engineering::Electrical and electronic engineering We propose a dynamic voltage scalable SRAM capable of efficient bit-interleaving in column to tolerate multiple-bits soft error when integrated with error correction codes (ECC). First, a 10T SRAM bitcell is proposed. It activates only intended bitcells so that stability problem of half-selected bitcells is completely eliminated and the power dissipation in half-selected columns is significantly reduced. Second, a configurable DVS scheme is employed to enable the bitcell to operate like differential 8T during super-threshold region which results in faster operation. The proposed SRAM can operate up to 1.2GHz at 1.2V using 65nm CMOS process. Third, a segmented column multiplex with low overhead is proposed, which greatly reduces the power dissipation due to the column control signals. Consequently, the write and read power dissipations are reduced by up to 40% and 67% respectively. Forth, a hierarchical read bitline is used to reduce the read bitline discharge delay variation due to local and global process variation in subthreshold region, which is a major portion of memory access time. Based on our simulation results, the worst case read bitline discharge delay is reduced by more than 12× at VDD of 0.3V. 2013-11-15T06:41:57Z 2019-12-06T22:12:09Z 2013-11-15T06:41:57Z 2019-12-06T22:12:09Z 2012 2012 Conference Paper Chen, J., Chong, K.-S., Gwee, B. H., & Chang, J. S. (2012). An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 1835-1838. https://hdl.handle.net/10356/106455 http://hdl.handle.net/10220/17694 http://dx.doi.org/10.1109/ISCAS.2012.6271625 en |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Chen, Junchao Chong, Kwen-Siong Gwee, Bah Hwee Chang, Joseph Sylvester An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability |
| title | An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability |
| title_full | An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability |
| title_fullStr | An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability |
| title_full_unstemmed | An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability |
| title_short | An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability |
| title_sort | ultra dynamic voltage scalable u dvs 10t sram with bit interleaving capability |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/106455 http://hdl.handle.net/10220/17694 http://dx.doi.org/10.1109/ISCAS.2012.6271625 |
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