An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability
We propose a dynamic voltage scalable SRAM capable of efficient bit-interleaving in column to tolerate multiple-bits soft error when integrated with error correction codes (ECC). First, a 10T SRAM bitcell is proposed. It activates only intended bitcells so that stability problem of half-selected bit...
| Main Authors: | , , , |
|---|---|
| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2013
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/106455 http://hdl.handle.net/10220/17694 http://dx.doi.org/10.1109/ISCAS.2012.6271625 |