High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters
This paper presents the design and implementation of a high resolution voltage-controlled oscillator (VCO)-based ΣΔADC for digital DC-DC converters. The proposed ADC adopts a robust VCO and a sixth-order delta-sigma modulation to attenuate the phase noise and output ripples. The delta-sigma modulati...
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2013
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| Online Access: | https://hdl.handle.net/10356/106782 http://hdl.handle.net/10220/17692 http://dx.doi.org/10.1142/S0218126612500624 |
| _version_ | 1824454817509015552 |
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| author | Foong, Huey Chian Tan, Meng Tong Zheng, Yuanjin |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Foong, Huey Chian Tan, Meng Tong Zheng, Yuanjin |
| author_sort | Foong, Huey Chian |
| collection | NTU |
| description | This paper presents the design and implementation of a high resolution voltage-controlled oscillator (VCO)-based ΣΔADC for digital DC-DC converters. The proposed ADC adopts a robust VCO and a sixth-order delta-sigma modulation to attenuate the phase noise and output ripples. The delta-sigma modulation is realized using a cascade of a second-order high-pass filter and a fourth-order band-stop noise shaping filter. Chopper modulation is further employed to reduce the effect of 1/f noise. These have significantly increased the signal-to-noise+distortion ratio (SNDR) and lead to high linearity. The proposed ADC was designed and fabricated using CMOS 0.18 μm process. From measurement, the differential and integral nonlinearities of the ADC are determined to be ±0.5 LSB and ±0.65 LSB, respectively. The SNDR of the ADC is 49 dB up to 500 kHz, which gives an ENOB of 8 bits and quantization step of 2 mV. The ADC also features a low power consumption of 120 μA and a small IC area of 0.18 mm^2. |
| first_indexed | 2025-02-19T03:28:20Z |
| format | Journal Article |
| id | ntu-10356/106782 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2025-02-19T03:28:20Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/1067822019-12-06T22:18:17Z High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters Foong, Huey Chian Tan, Meng Tong Zheng, Yuanjin School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering This paper presents the design and implementation of a high resolution voltage-controlled oscillator (VCO)-based ΣΔADC for digital DC-DC converters. The proposed ADC adopts a robust VCO and a sixth-order delta-sigma modulation to attenuate the phase noise and output ripples. The delta-sigma modulation is realized using a cascade of a second-order high-pass filter and a fourth-order band-stop noise shaping filter. Chopper modulation is further employed to reduce the effect of 1/f noise. These have significantly increased the signal-to-noise+distortion ratio (SNDR) and lead to high linearity. The proposed ADC was designed and fabricated using CMOS 0.18 μm process. From measurement, the differential and integral nonlinearities of the ADC are determined to be ±0.5 LSB and ±0.65 LSB, respectively. The SNDR of the ADC is 49 dB up to 500 kHz, which gives an ENOB of 8 bits and quantization step of 2 mV. The ADC also features a low power consumption of 120 μA and a small IC area of 0.18 mm^2. 2013-11-15T06:39:42Z 2019-12-06T22:18:17Z 2013-11-15T06:39:42Z 2019-12-06T22:18:17Z 2012 2012 Journal Article Foong, H.C., Tan M.T., & Zheng Y. (2012). High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters. Journal of Circuits, Systems and Computers, 21(07), 1250062-. https://hdl.handle.net/10356/106782 http://hdl.handle.net/10220/17692 http://dx.doi.org/10.1142/S0218126612500624 en Journal of circuits, systems and computers |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Foong, Huey Chian Tan, Meng Tong Zheng, Yuanjin High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters |
| title | High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters |
| title_full | High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters |
| title_fullStr | High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters |
| title_full_unstemmed | High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters |
| title_short | High linearity 8-bit VCO-based cascaded ΣΔADC for digital DC-DC converters |
| title_sort | high linearity 8 bit vco based cascaded σδadc for digital dc dc converters |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/106782 http://hdl.handle.net/10220/17692 http://dx.doi.org/10.1142/S0218126612500624 |
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