Low-power, adaptive neuromorphic systems : recent progress and future directions
In this paper, we present a survey of recent works in developing neuromorphic or neuro-inspired hardware systems. In particular, we focus on those systems which can either learn from data in an unsupervised or online supervised manner. We present algorithms and architectures developed specially to s...
| Main Authors: | , , , , , , |
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| Format: | Journal Article |
| Language: | English |
| Published: |
2019
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| Online Access: | https://hdl.handle.net/10356/106809 http://hdl.handle.net/10220/49651 http://dx.doi.org/10.1109/JETCAS.2018.2816339 |
| _version_ | 1811685996658425856 |
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| author | Basu, Arindam Acharya, Jyotibdha Karnik, Tanay Liu, Huichu Li, Hai Seo, Jae-Sun Song, Chang |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Basu, Arindam Acharya, Jyotibdha Karnik, Tanay Liu, Huichu Li, Hai Seo, Jae-Sun Song, Chang |
| author_sort | Basu, Arindam |
| collection | NTU |
| description | In this paper, we present a survey of recent works in developing neuromorphic or neuro-inspired hardware systems. In particular, we focus on those systems which can either learn from data in an unsupervised or online supervised manner. We present algorithms and architectures developed specially to support on-chip learning. Emphasis is placed on hardware friendly modifications of standard algorithms, such as backpropagation, as well as novel algorithms, such as structural plasticity, developed specially for low-resolution synapses. We cover works related to both spike-based and more traditional non-spike-based algorithms. This is followed by developments in novel devices, such as floating-gate MOS, memristors, and spintronic devices. CMOS circuit innovations for on-chip learning and CMOS interface circuits for post-CMOS devices, such as memristors, are presented. Common architectures, such as crossbar or island style arrays, are discussed, along with their relative merits and demerits. Finally, we present some possible applications of neuromorphic hardware, such as brain-machine interfaces, robotics, etc., and identify future research trends in the field. |
| first_indexed | 2024-10-01T04:53:24Z |
| format | Journal Article |
| id | ntu-10356/106809 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:53:24Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/1068092019-12-06T22:18:52Z Low-power, adaptive neuromorphic systems : recent progress and future directions Basu, Arindam Acharya, Jyotibdha Karnik, Tanay Liu, Huichu Li, Hai Seo, Jae-Sun Song, Chang School of Electrical and Electronic Engineering Neuromorphics Engineering::Electrical and electronic engineering Hardware In this paper, we present a survey of recent works in developing neuromorphic or neuro-inspired hardware systems. In particular, we focus on those systems which can either learn from data in an unsupervised or online supervised manner. We present algorithms and architectures developed specially to support on-chip learning. Emphasis is placed on hardware friendly modifications of standard algorithms, such as backpropagation, as well as novel algorithms, such as structural plasticity, developed specially for low-resolution synapses. We cover works related to both spike-based and more traditional non-spike-based algorithms. This is followed by developments in novel devices, such as floating-gate MOS, memristors, and spintronic devices. CMOS circuit innovations for on-chip learning and CMOS interface circuits for post-CMOS devices, such as memristors, are presented. Common architectures, such as crossbar or island style arrays, are discussed, along with their relative merits and demerits. Finally, we present some possible applications of neuromorphic hardware, such as brain-machine interfaces, robotics, etc., and identify future research trends in the field. Published version 2019-08-15T05:48:26Z 2019-12-06T22:18:52Z 2019-08-15T05:48:26Z 2019-12-06T22:18:52Z 2018 Journal Article Basu, A., Acharya, J., Karnik, T., Liu, H., Li, H., Seo, J.-S., & Song, C. (2018). Low-power, adaptive neuromorphic systems : recent progress and future directions. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8(1), 6-27. doi:10.1109/JETCAS.2018.2816339 2156-3357 https://hdl.handle.net/10356/106809 http://hdl.handle.net/10220/49651 http://dx.doi.org/10.1109/JETCAS.2018.2816339 en IEEE Journal of Emerging and Selected Topics in Circuits and Systems © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/JETCAS.2018.2816339 22 p. application/pdf |
| spellingShingle | Neuromorphics Engineering::Electrical and electronic engineering Hardware Basu, Arindam Acharya, Jyotibdha Karnik, Tanay Liu, Huichu Li, Hai Seo, Jae-Sun Song, Chang Low-power, adaptive neuromorphic systems : recent progress and future directions |
| title | Low-power, adaptive neuromorphic systems : recent progress and future directions |
| title_full | Low-power, adaptive neuromorphic systems : recent progress and future directions |
| title_fullStr | Low-power, adaptive neuromorphic systems : recent progress and future directions |
| title_full_unstemmed | Low-power, adaptive neuromorphic systems : recent progress and future directions |
| title_short | Low-power, adaptive neuromorphic systems : recent progress and future directions |
| title_sort | low power adaptive neuromorphic systems recent progress and future directions |
| topic | Neuromorphics Engineering::Electrical and electronic engineering Hardware |
| url | https://hdl.handle.net/10356/106809 http://hdl.handle.net/10220/49651 http://dx.doi.org/10.1109/JETCAS.2018.2816339 |
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