Robust doublet STDP in a floating-gate synapse
Learning in a neural network typically happens with the modification or plasticity of synaptic weight. Thus the plasticity rule which modifies the synaptic strength based on the timing difference between the pre- and post-synaptic spike occurrence is termed as Spike Time Dependent Plasticity (STDP)....
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| Format: | Conference Paper |
| Language: | English |
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2015
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| Online Access: | https://hdl.handle.net/10356/106928 http://hdl.handle.net/10220/25141 http://dx.doi.org/10.1109/IJCNN.2014.6889631 |
| _version_ | 1811677927908048896 |
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| author | Gopalakrishnan, Roshan Basu, Arindam |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Gopalakrishnan, Roshan Basu, Arindam |
| author_sort | Gopalakrishnan, Roshan |
| collection | NTU |
| description | Learning in a neural network typically happens with the modification or plasticity of synaptic weight. Thus the plasticity rule which modifies the synaptic strength based on the timing difference between the pre- and post-synaptic spike occurrence is termed as Spike Time Dependent Plasticity (STDP). This paper describes the neuromorphic VLSI implementation of a synapse utilizing a single floating-gate (FG) transistor that can be used to store a weight in a nonvolatile manner and demonstrate biological learning rules such as Long-Term Potentiation (LTP), Long-Term Depression (LTD) and STDP. The experimental STDP plot of a FG synapse (change in weight against Δt tpost tpre) from previous studies shows a depression instead of potentiation at some range of positive values of Δt for a wide set of parameters. In this paper, we present a simple solution based on changing control gate waveforms of the FG device that makes the weight change conform closely with biological observations over a wide range of parameters. We show results from a theoretical model to illustrate the effects of the modified waveform. The experimental results from a FG synapse fabricated in AMS 0.35μm CMOS process design are also presented to justify the claim. |
| first_indexed | 2024-10-01T02:45:09Z |
| format | Conference Paper |
| id | ntu-10356/106928 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:45:09Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/1069282019-12-06T22:21:16Z Robust doublet STDP in a floating-gate synapse Gopalakrishnan, Roshan Basu, Arindam School of Electrical and Electronic Engineering 2014 International Joint Conference on Neural Networks (IJCNN) DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems Learning in a neural network typically happens with the modification or plasticity of synaptic weight. Thus the plasticity rule which modifies the synaptic strength based on the timing difference between the pre- and post-synaptic spike occurrence is termed as Spike Time Dependent Plasticity (STDP). This paper describes the neuromorphic VLSI implementation of a synapse utilizing a single floating-gate (FG) transistor that can be used to store a weight in a nonvolatile manner and demonstrate biological learning rules such as Long-Term Potentiation (LTP), Long-Term Depression (LTD) and STDP. The experimental STDP plot of a FG synapse (change in weight against Δt tpost tpre) from previous studies shows a depression instead of potentiation at some range of positive values of Δt for a wide set of parameters. In this paper, we present a simple solution based on changing control gate waveforms of the FG device that makes the weight change conform closely with biological observations over a wide range of parameters. We show results from a theoretical model to illustrate the effects of the modified waveform. The experimental results from a FG synapse fabricated in AMS 0.35μm CMOS process design are also presented to justify the claim. Accepted version 2015-03-02T06:38:57Z 2019-12-06T22:21:16Z 2015-03-02T06:38:57Z 2019-12-06T22:21:16Z 2014 2014 Conference Paper Gopalakrishnan, R., & Basu, A. (2014). Robust doublet STDP in a floating-gate synapse. 2014 International Joint Conference on Neural Networks (IJCNN), 4296-4301. https://hdl.handle.net/10356/106928 http://hdl.handle.net/10220/25141 http://dx.doi.org/10.1109/IJCNN.2014.6889631 en © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [Article DOI: http://dx.doi.org/10.1109/IJCNN.2014.6889631]. 6 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems Gopalakrishnan, Roshan Basu, Arindam Robust doublet STDP in a floating-gate synapse |
| title | Robust doublet STDP in a floating-gate synapse |
| title_full | Robust doublet STDP in a floating-gate synapse |
| title_fullStr | Robust doublet STDP in a floating-gate synapse |
| title_full_unstemmed | Robust doublet STDP in a floating-gate synapse |
| title_short | Robust doublet STDP in a floating-gate synapse |
| title_sort | robust doublet stdp in a floating gate synapse |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems |
| url | https://hdl.handle.net/10356/106928 http://hdl.handle.net/10220/25141 http://dx.doi.org/10.1109/IJCNN.2014.6889631 |
| work_keys_str_mv | AT gopalakrishnanroshan robustdoubletstdpinafloatinggatesynapse AT basuarindam robustdoubletstdpinafloatinggatesynapse |