Design of high performance quarter-micron retrograde well P-channel MOSFET
This thesis presents the design and optimization through fabrication and simulation of quarter-micron surface-channel pMOSFETs for low power, high speed applications. The high performance pMOSFET is realized by careful design of the channel, well and source/drain doping profile. The main features of...
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
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2008
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| Online Access: | http://hdl.handle.net/10356/13355 |
| _version_ | 1826119938764439552 |
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| author | Swe, Toe Naing. |
| author2 | Yeo, Kiat Seng |
| author_facet | Yeo, Kiat Seng Swe, Toe Naing. |
| author_sort | Swe, Toe Naing. |
| collection | NTU |
| description | This thesis presents the design and optimization through fabrication and simulation of quarter-micron surface-channel pMOSFETs for low power, high speed applications. The high performance pMOSFET is realized by careful design of the channel, well and source/drain doping profile. The main features of the fabricated devices are non-uniform channel doping, high energy deep retrograde well, p+-polysilicon gate approach and the LDD source-drain structure. |
| first_indexed | 2024-10-01T05:08:19Z |
| format | Thesis |
| id | ntu-10356/13355 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:08:19Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | ntu-10356/133552023-07-04T16:01:29Z Design of high performance quarter-micron retrograde well P-channel MOSFET Swe, Toe Naing. Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits This thesis presents the design and optimization through fabrication and simulation of quarter-micron surface-channel pMOSFETs for low power, high speed applications. The high performance pMOSFET is realized by careful design of the channel, well and source/drain doping profile. The main features of the fabricated devices are non-uniform channel doping, high energy deep retrograde well, p+-polysilicon gate approach and the LDD source-drain structure. Master of Engineering 2008-08-01T04:56:05Z 2008-10-20T07:26:16Z 2008-08-01T04:56:05Z 2008-10-20T07:26:16Z 1999 1999 Thesis http://hdl.handle.net/10356/13355 en 137.p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Swe, Toe Naing. Design of high performance quarter-micron retrograde well P-channel MOSFET |
| title | Design of high performance quarter-micron retrograde well P-channel MOSFET |
| title_full | Design of high performance quarter-micron retrograde well P-channel MOSFET |
| title_fullStr | Design of high performance quarter-micron retrograde well P-channel MOSFET |
| title_full_unstemmed | Design of high performance quarter-micron retrograde well P-channel MOSFET |
| title_short | Design of high performance quarter-micron retrograde well P-channel MOSFET |
| title_sort | design of high performance quarter micron retrograde well p channel mosfet |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| url | http://hdl.handle.net/10356/13355 |
| work_keys_str_mv | AT swetoenaing designofhighperformancequartermicronretrogradewellpchannelmosfet |