Low power CMOS memory circuit design
Two novel SRAM is proposed and simulated with TSMC 40nm technology. Both novel 10T SRAM is designed to be used under low power supply, with features such as low power consumption and high reading static noise margin. Both proposed SRAM can operate under supply voltage as low as 0.31V. Under this sup...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
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Nanyang Technological University
2020
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| Online Access: | https://hdl.handle.net/10356/138635 |
| _version_ | 1826121420921372672 |
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| author | Foo, Chee Heng |
| author2 | Lau K T |
| author_facet | Lau K T Foo, Chee Heng |
| author_sort | Foo, Chee Heng |
| collection | NTU |
| description | Two novel SRAM is proposed and simulated with TSMC 40nm technology. Both novel 10T SRAM is designed to be used under low power supply, with features such as low power consumption and high reading static noise margin. Both proposed SRAM can operate under supply voltage as low as 0.31V. Under this supply voltage, it has read static noise margin of 107 mV, which is more than three times better compared to the conventional 6T SRAM. The first novel 10T SRAM is designed using multi-threshold voltage technique, where the four reading transistors have higher threshold than the other transistors. The second novel 10T SRAM use transistors with same threshold voltage. The first novel 10T SRAM has improvement in read delay of 184.1 ns and overall power consumption compared to 9T SRAM in previous research which also uses multi-threshold voltage technique. The second novel 10T SRAM has significant improvement in read delay, which is only 16.34 ns, with trade-off of less than 10% increase in power consumption. |
| first_indexed | 2024-10-01T05:32:02Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/138635 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:32:02Z |
| publishDate | 2020 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1386352023-07-07T18:08:43Z Low power CMOS memory circuit design Foo, Chee Heng Lau K T School of Electrical and Electronic Engineering ektlau@ntu.edu.sg Engineering::Electrical and electronic engineering::Integrated circuits Two novel SRAM is proposed and simulated with TSMC 40nm technology. Both novel 10T SRAM is designed to be used under low power supply, with features such as low power consumption and high reading static noise margin. Both proposed SRAM can operate under supply voltage as low as 0.31V. Under this supply voltage, it has read static noise margin of 107 mV, which is more than three times better compared to the conventional 6T SRAM. The first novel 10T SRAM is designed using multi-threshold voltage technique, where the four reading transistors have higher threshold than the other transistors. The second novel 10T SRAM use transistors with same threshold voltage. The first novel 10T SRAM has improvement in read delay of 184.1 ns and overall power consumption compared to 9T SRAM in previous research which also uses multi-threshold voltage technique. The second novel 10T SRAM has significant improvement in read delay, which is only 16.34 ns, with trade-off of less than 10% increase in power consumption. Bachelor of Engineering (Electrical and Electronic Engineering) 2020-05-11T05:39:02Z 2020-05-11T05:39:02Z 2020 Final Year Project (FYP) https://hdl.handle.net/10356/138635 en A2010-191 application/pdf Nanyang Technological University |
| spellingShingle | Engineering::Electrical and electronic engineering::Integrated circuits Foo, Chee Heng Low power CMOS memory circuit design |
| title | Low power CMOS memory circuit design |
| title_full | Low power CMOS memory circuit design |
| title_fullStr | Low power CMOS memory circuit design |
| title_full_unstemmed | Low power CMOS memory circuit design |
| title_short | Low power CMOS memory circuit design |
| title_sort | low power cmos memory circuit design |
| topic | Engineering::Electrical and electronic engineering::Integrated circuits |
| url | https://hdl.handle.net/10356/138635 |
| work_keys_str_mv | AT foocheeheng lowpowercmosmemorycircuitdesign |