Low power CMOS memory circuit design
Two novel SRAM is proposed and simulated with TSMC 40nm technology. Both novel 10T SRAM is designed to be used under low power supply, with features such as low power consumption and high reading static noise margin. Both proposed SRAM can operate under supply voltage as low as 0.31V. Under this sup...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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Nanyang Technological University
2020
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| Online Access: | https://hdl.handle.net/10356/138635 |