Development of electrical, electronic & information system

SOI technologies offer solutions to low power, high performance applications. The key device-architecture issue is the choice between partially depleted and fully depleted devices. While each structure has pros and cons, the choice needs to be balanced between process complexity and performance. The...

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Bibliographic Details
Main Authors: Gwee, Bah Hwee., Sng, Kenneth Eng Kian., So, Ping Lam.
Other Authors: School of Electrical and Electronic Engineering
Format: Research Report
Language:English
Published: 2008
Subjects:
Online Access:http://hdl.handle.net/10356/14242
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author Gwee, Bah Hwee.
Sng, Kenneth Eng Kian.
So, Ping Lam.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Gwee, Bah Hwee.
Sng, Kenneth Eng Kian.
So, Ping Lam.
author_sort Gwee, Bah Hwee.
collection NTU
description SOI technologies offer solutions to low power, high performance applications. The key device-architecture issue is the choice between partially depleted and fully depleted devices. While each structure has pros and cons, the choice needs to be balanced between process complexity and performance. Thereafter, engineers have ventured into some non-classical transistor structures will likely take over due to their delivery of higher performance with lower leakage than traditional scaled SOI CMOS approaches. The possibility of using a back gate have sparked a large research activity in the field of novel SOI devices. Among all other multiple gate design, it is well known that Gate-All-Around (GAA) MOSFET offers the most attractive properties for digital application. GAA MOSFET is being examined as extension of planar CMOS technology with potential to increase performance and packing density over the conventional technique.
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spelling ntu-10356/142422023-03-04T03:23:29Z Development of electrical, electronic & information system Gwee, Bah Hwee. Sng, Kenneth Eng Kian. So, Ping Lam. School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic systems SOI technologies offer solutions to low power, high performance applications. The key device-architecture issue is the choice between partially depleted and fully depleted devices. While each structure has pros and cons, the choice needs to be balanced between process complexity and performance. Thereafter, engineers have ventured into some non-classical transistor structures will likely take over due to their delivery of higher performance with lower leakage than traditional scaled SOI CMOS approaches. The possibility of using a back gate have sparked a large research activity in the field of novel SOI devices. Among all other multiple gate design, it is well known that Gate-All-Around (GAA) MOSFET offers the most attractive properties for digital application. GAA MOSFET is being examined as extension of planar CMOS technology with potential to increase performance and packing density over the conventional technique. 2008-11-06T08:15:10Z 2008-11-06T08:15:10Z 2007 2007 Research Report http://hdl.handle.net/10356/14242 en 134 p. application/pdf
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Gwee, Bah Hwee.
Sng, Kenneth Eng Kian.
So, Ping Lam.
Development of electrical, electronic & information system
title Development of electrical, electronic & information system
title_full Development of electrical, electronic & information system
title_fullStr Development of electrical, electronic & information system
title_full_unstemmed Development of electrical, electronic & information system
title_short Development of electrical, electronic & information system
title_sort development of electrical electronic information system
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
url http://hdl.handle.net/10356/14242
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