A fast approach for generating efficient parsers on FPGAs
The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets-this is the precondition for further processing and finally for...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2020
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/142820 |
| _version_ | 1826121877337145344 |
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| author | Cao, Zhuang Zhang, Huiguo Li, Junnan Wen, Mei Zhang, Chunyuan |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Cao, Zhuang Zhang, Huiguo Li, Junnan Wen, Mei Zhang, Chunyuan |
| author_sort | Cao, Zhuang |
| collection | NTU |
| description | The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets-this is the precondition for further processing and finally forwarding these packets. This paper presents a framework designed to transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays (FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler. The hardware architecture comprises many components with varying functionality, each of which has its own optimized VHDL template. By using the output of a standard frontend P4 compiler, our proposed compiler extracts the parameters and relationships from within the used components, which can then be mapped to corresponding templates by configuring, optimizing, and instantiating them. Finally, these templates are connected to output VHDL code. When a prototype of this framework is implemented and evaluated, the results demonstrate that the throughputs of the generated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with state-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when similar amounts of resources are being used. |
| first_indexed | 2024-10-01T05:39:20Z |
| format | Journal Article |
| id | ntu-10356/142820 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:39:20Z |
| publishDate | 2020 |
| record_format | dspace |
| spelling | ntu-10356/1428202020-07-03T01:12:50Z A fast approach for generating efficient parsers on FPGAs Cao, Zhuang Zhang, Huiguo Li, Junnan Wen, Mei Zhang, Chunyuan School of Computer Science and Engineering Engineering::Computer science and engineering Packet Parser Pipeline The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets-this is the precondition for further processing and finally forwarding these packets. This paper presents a framework designed to transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays (FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler. The hardware architecture comprises many components with varying functionality, each of which has its own optimized VHDL template. By using the output of a standard frontend P4 compiler, our proposed compiler extracts the parameters and relationships from within the used components, which can then be mapped to corresponding templates by configuring, optimizing, and instantiating them. Finally, these templates are connected to output VHDL code. When a prototype of this framework is implemented and evaluated, the results demonstrate that the throughputs of the generated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with state-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when similar amounts of resources are being used. Published version 2020-07-03T01:12:50Z 2020-07-03T01:12:50Z 2019 Journal Article Cao, Z., Zhang, H., Li, J., Wen, M., & Zhang, C. (2019). A fast approach for generating efficient parsers on FPGAs. Symmetry, 11(10), 1265-. doi:10.3390/sym11101265 2073-8994 https://hdl.handle.net/10356/142820 10.3390/sym11101265 2-s2.0-85074301948 10 11 en Symmetry © 2019 The Authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). application/pdf |
| spellingShingle | Engineering::Computer science and engineering Packet Parser Pipeline Cao, Zhuang Zhang, Huiguo Li, Junnan Wen, Mei Zhang, Chunyuan A fast approach for generating efficient parsers on FPGAs |
| title | A fast approach for generating efficient parsers on FPGAs |
| title_full | A fast approach for generating efficient parsers on FPGAs |
| title_fullStr | A fast approach for generating efficient parsers on FPGAs |
| title_full_unstemmed | A fast approach for generating efficient parsers on FPGAs |
| title_short | A fast approach for generating efficient parsers on FPGAs |
| title_sort | fast approach for generating efficient parsers on fpgas |
| topic | Engineering::Computer science and engineering Packet Parser Pipeline |
| url | https://hdl.handle.net/10356/142820 |
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