Threshold-guided design and optimization for Harris corner detector architecture
High-speed corner detection is an essential step in many real-time computer vision applications, e.g., object recognition, motion analysis, and stereo matching. Hardware implementation of corner detection algorithms, such as the Harris corner detector (HCD) has become a viable solution for meeting r...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2020
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| Online Access: | https://hdl.handle.net/10356/142931 |
| _version_ | 1826121084886319104 |
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| author | Jasani, Bhavan Ashwin Lam, Siew-Kei Meher, Pramod Kumar Wu, Meiqing |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Jasani, Bhavan Ashwin Lam, Siew-Kei Meher, Pramod Kumar Wu, Meiqing |
| author_sort | Jasani, Bhavan Ashwin |
| collection | NTU |
| description | High-speed corner detection is an essential step in many real-time computer vision applications, e.g., object recognition, motion analysis, and stereo matching. Hardware implementation of corner detection algorithms, such as the Harris corner detector (HCD) has become a viable solution for meeting real-time requirements of the applications. A major challenge lies in the design of power, energy and area efficient architectures that can be deployed in tightly constrained embedded systems while still meeting real-time requirements. In this paper, we proposed a bit-width optimization strategy for designing hardware-efficient HCD that exploits the thresholding step in the algorithm to determine interest points from the corner responses. The proposed strategy relies on the threshold as a guide to truncate the bit-widths of the operators at various stages of the HCD pipeline with only marginal loss of accuracy. Synthesis results based on 65-nm CMOS technology show that the proposed strategy leads to power-delay reduction of 35.2%, and area reduction of 35.4% over the baseline implementation. In addition, through careful retiming, the proposed implementation achieves over 2.2 times increase in maximum frequency while achieving an area reduction of 35.1% and power-delay reduction of 35.7% over the baseline implementation. Finally, we performed repeatability tests to show that the optimized HCD architecture achieves comparable accuracy with the baseline implementation (average decrease of repeatability is less than 0.6%). |
| first_indexed | 2024-10-01T05:26:58Z |
| format | Journal Article |
| id | ntu-10356/142931 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:26:58Z |
| publishDate | 2020 |
| record_format | dspace |
| spelling | ntu-10356/1429312020-07-14T01:43:49Z Threshold-guided design and optimization for Harris corner detector architecture Jasani, Bhavan Ashwin Lam, Siew-Kei Meher, Pramod Kumar Wu, Meiqing School of Computer Science and Engineering Hardware and Embedded Systems Laboratory Engineering::Computer science and engineering Corner Detection Hardware Acceleration High-speed corner detection is an essential step in many real-time computer vision applications, e.g., object recognition, motion analysis, and stereo matching. Hardware implementation of corner detection algorithms, such as the Harris corner detector (HCD) has become a viable solution for meeting real-time requirements of the applications. A major challenge lies in the design of power, energy and area efficient architectures that can be deployed in tightly constrained embedded systems while still meeting real-time requirements. In this paper, we proposed a bit-width optimization strategy for designing hardware-efficient HCD that exploits the thresholding step in the algorithm to determine interest points from the corner responses. The proposed strategy relies on the threshold as a guide to truncate the bit-widths of the operators at various stages of the HCD pipeline with only marginal loss of accuracy. Synthesis results based on 65-nm CMOS technology show that the proposed strategy leads to power-delay reduction of 35.2%, and area reduction of 35.4% over the baseline implementation. In addition, through careful retiming, the proposed implementation achieves over 2.2 times increase in maximum frequency while achieving an area reduction of 35.1% and power-delay reduction of 35.7% over the baseline implementation. Finally, we performed repeatability tests to show that the optimized HCD architecture achieves comparable accuracy with the baseline implementation (average decrease of repeatability is less than 0.6%). 2020-07-14T01:43:49Z 2020-07-14T01:43:49Z 2017 Journal Article Jasani, B. A., Lam, S.-K., Meher, P. K., & Wu, M. (2018). Threshold-guided design and optimization for Harris corner detector architecture. IEEE Transactions on Circuits and Systems for Video Technology, 28(12), 3516-3526. doi:10.1109/TCSVT.2017.2757998 1051-8215 https://hdl.handle.net/10356/142931 10.1109/TCSVT.2017.2757998 2-s2.0-85030769007 12 28 3516 3526 en IEEE Transactions on Circuits and Systems for Video Technology © 2017 IEEE. All rights reserved. |
| spellingShingle | Engineering::Computer science and engineering Corner Detection Hardware Acceleration Jasani, Bhavan Ashwin Lam, Siew-Kei Meher, Pramod Kumar Wu, Meiqing Threshold-guided design and optimization for Harris corner detector architecture |
| title | Threshold-guided design and optimization for Harris corner detector architecture |
| title_full | Threshold-guided design and optimization for Harris corner detector architecture |
| title_fullStr | Threshold-guided design and optimization for Harris corner detector architecture |
| title_full_unstemmed | Threshold-guided design and optimization for Harris corner detector architecture |
| title_short | Threshold-guided design and optimization for Harris corner detector architecture |
| title_sort | threshold guided design and optimization for harris corner detector architecture |
| topic | Engineering::Computer science and engineering Corner Detection Hardware Acceleration |
| url | https://hdl.handle.net/10356/142931 |
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