14.3 A 43pJ/cycle non-volatile microcontroller with 4.7μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resillence techniques
Non-volatility is emerging as an essential on-chip memory characteristic across a wide range of application domains, from edge nodes for the Internet of Things (IoT) to large computing clusters. On-chip non-volatile memory (NVM) is critical for low-energy operation, real-time responses, privacy and...
| Main Authors: | , , , , , , , , , , , , , , , |
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| Format: | Conference Paper |
| Language: | English |
| Published: |
2020
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/143358 |
| _version_ | 1826122052980965376 |
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| author | Wu, Tony F. Le, Binh Q. Radway, Robert Bartolo, Andrew Hwang, William Jeong, Seungbin Li, Haitong Tandon, Pulkit Vianello, Elisa Vivet, Pascal Nowak, Etienne Wootters, Mary K. Wong, Philip H.-S. Mohamed M. Sabry Aly Beigne, Edith Mitra, Subhasish |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Wu, Tony F. Le, Binh Q. Radway, Robert Bartolo, Andrew Hwang, William Jeong, Seungbin Li, Haitong Tandon, Pulkit Vianello, Elisa Vivet, Pascal Nowak, Etienne Wootters, Mary K. Wong, Philip H.-S. Mohamed M. Sabry Aly Beigne, Edith Mitra, Subhasish |
| author_sort | Wu, Tony F. |
| collection | NTU |
| description | Non-volatility is emerging as an essential on-chip memory characteristic across a wide range of application domains, from edge nodes for the Internet of Things (IoT) to large computing clusters. On-chip non-volatile memory (NVM) is critical for low-energy operation, real-time responses, privacy and security, operation in unpredictable environments, and fault-tolerance [1]. Existing on-chip NVMs (e.g., Flash, FRAM, EEPROM) suffer from high read/write energy/latency, density, and integration challenges [1]. For example, an ideal IoT edge system would employ fine-grained temporal power gating (i.e., shutdown) between active modes. However, existing on-chip Flash can have long latencies (> 23 ms latency for erase followed by write), while inter-sample arrival times can be short (e.g., 2ms in [2]). |
| first_indexed | 2024-10-01T05:42:12Z |
| format | Conference Paper |
| id | ntu-10356/143358 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:42:12Z |
| publishDate | 2020 |
| record_format | dspace |
| spelling | ntu-10356/1433582020-08-26T06:12:08Z 14.3 A 43pJ/cycle non-volatile microcontroller with 4.7μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resillence techniques Wu, Tony F. Le, Binh Q. Radway, Robert Bartolo, Andrew Hwang, William Jeong, Seungbin Li, Haitong Tandon, Pulkit Vianello, Elisa Vivet, Pascal Nowak, Etienne Wootters, Mary K. Wong, Philip H.-S. Mohamed M. Sabry Aly Beigne, Edith Mitra, Subhasish School of Computer Science and Engineering 2019 IEEE International Solid-State Circuits Conference (ISSCC 2019) Engineering::Computer science and engineering System-On-Chip Nonvolatile Memory Non-volatility is emerging as an essential on-chip memory characteristic across a wide range of application domains, from edge nodes for the Internet of Things (IoT) to large computing clusters. On-chip non-volatile memory (NVM) is critical for low-energy operation, real-time responses, privacy and security, operation in unpredictable environments, and fault-tolerance [1]. Existing on-chip NVMs (e.g., Flash, FRAM, EEPROM) suffer from high read/write energy/latency, density, and integration challenges [1]. For example, an ideal IoT edge system would employ fine-grained temporal power gating (i.e., shutdown) between active modes. However, existing on-chip Flash can have long latencies (> 23 ms latency for erase followed by write), while inter-sample arrival times can be short (e.g., 2ms in [2]). Accepted version Work supported in part by DARPA, NSF/NRI/GRC E2CDA, and the Stanford SystemX Alliance. 2020-08-26T06:12:08Z 2020-08-26T06:12:08Z 2019 Conference Paper Wu, T. F., Le, B. Q., Radway, R., Bartolo, A., Hwang, W., Jeong, S., ... Mitra, S. (2019). 14.3 A 43pJ/cycle non-volatile microcontroller with 4.7μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resillence techniques. Proceedings of 2019 IEEE International Solid-State Circuits Conference (ISSCC 2019), 226-228. doi:10.1109/ISSCC.2019.8662402 978-1-5386-8532-7 https://hdl.handle.net/10356/143358 10.1109/ISSCC.2019.8662402 2-s2.0-85063537157 226 228 en © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/ISSCC.2019.8662402. application/pdf |
| spellingShingle | Engineering::Computer science and engineering System-On-Chip Nonvolatile Memory Wu, Tony F. Le, Binh Q. Radway, Robert Bartolo, Andrew Hwang, William Jeong, Seungbin Li, Haitong Tandon, Pulkit Vianello, Elisa Vivet, Pascal Nowak, Etienne Wootters, Mary K. Wong, Philip H.-S. Mohamed M. Sabry Aly Beigne, Edith Mitra, Subhasish 14.3 A 43pJ/cycle non-volatile microcontroller with 4.7μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resillence techniques |
| title | 14.3 A 43pJ/cycle non-volatile microcontroller with 4.7μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resillence techniques |
| title_full | 14.3 A 43pJ/cycle non-volatile microcontroller with 4.7μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resillence techniques |
| title_fullStr | 14.3 A 43pJ/cycle non-volatile microcontroller with 4.7μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resillence techniques |
| title_full_unstemmed | 14.3 A 43pJ/cycle non-volatile microcontroller with 4.7μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resillence techniques |
| title_short | 14.3 A 43pJ/cycle non-volatile microcontroller with 4.7μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resillence techniques |
| title_sort | 14 3 a 43pj cycle non volatile microcontroller with 4 7μs shutdown wake up integrating 2 3 bit cell resistive ram and resillence techniques |
| topic | Engineering::Computer science and engineering System-On-Chip Nonvolatile Memory |
| url | https://hdl.handle.net/10356/143358 |
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