A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology
A fully integrated 93.4-104.8-GHz 57-mW fractional-N cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional-N PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition r...
| Main Authors: | , , , , , , , , |
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| Format: | Journal Article |
| Language: | English |
| Published: |
2020
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| Online Access: | https://hdl.handle.net/10356/144845 |
| _version_ | 1824455094220881920 |
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| author | Yi, Xiang Liang, Zhipeng Feng, Guangyin Meng, Fanyi Wang, Cheng Li, Chenyang Yang, Kaituo Liu, Bei Boon, Chirn Chye |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Yi, Xiang Liang, Zhipeng Feng, Guangyin Meng, Fanyi Wang, Cheng Li, Chenyang Yang, Kaituo Liu, Bei Boon, Chirn Chye |
| author_sort | Yi, Xiang |
| collection | NTU |
| description | A fully integrated 93.4-104.8-GHz 57-mW fractional-N cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional-N PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition range are achieved simultaneously. The transformer-based true in-phase injection coupled technique is adopted in the QVCO to obtain both low phase noise and low-power consumption. The proposed cascaded PLL was fabricated in a 65-nm CMOS technology with silicon size of 0.88 mm 2 . The measured phase noise of QVCO and PLL is -113.26 and -106.63 dBc/Hz at 10-MHz offset, respectively. The FOM and FOMT of the QVCO at 10-MHz offset are -178.4 and -180.0 dBc/Hz, respectively. The frequency resolution of the 100-GHz output is less than 3.6 kHz. |
| first_indexed | 2025-02-19T03:32:44Z |
| format | Journal Article |
| id | ntu-10356/144845 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2025-02-19T03:32:44Z |
| publishDate | 2020 |
| record_format | dspace |
| spelling | ntu-10356/1448452020-11-30T02:42:18Z A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology Yi, Xiang Liang, Zhipeng Feng, Guangyin Meng, Fanyi Wang, Cheng Li, Chenyang Yang, Kaituo Liu, Bei Boon, Chirn Chye School of Electrical and Electronic Engineering VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering Cascaded Phase-locked Loop (PLL) Frequency Synthesizer A fully integrated 93.4-104.8-GHz 57-mW fractional-N cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional-N PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition range are achieved simultaneously. The transformer-based true in-phase injection coupled technique is adopted in the QVCO to obtain both low phase noise and low-power consumption. The proposed cascaded PLL was fabricated in a 65-nm CMOS technology with silicon size of 0.88 mm 2 . The measured phase noise of QVCO and PLL is -113.26 and -106.63 dBc/Hz at 10-MHz offset, respectively. The FOM and FOMT of the QVCO at 10-MHz offset are -178.4 and -180.0 dBc/Hz, respectively. The frequency resolution of the 100-GHz output is less than 3.6 kHz. Accepted version 2020-11-30T02:10:53Z 2020-11-30T02:10:53Z 2019 Journal Article Yi, X., Liang, Z., Feng, G., Meng, F., Wang, C., Li, C., ... Boon, C. C. (2019). A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology. IEEE Transactions on Microwave Theory and Techniques, 67(6), 2370-2381. doi:10.1109/TMTT.2019.2906614 1557-9670 https://hdl.handle.net/10356/144845 10.1109/TMTT.2019.2906614 6 67 2370 2381 en IEEE Transactions on Microwave Theory and Techniques © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TMTT.2019.2906614 application/pdf |
| spellingShingle | Engineering::Electrical and electronic engineering Cascaded Phase-locked Loop (PLL) Frequency Synthesizer Yi, Xiang Liang, Zhipeng Feng, Guangyin Meng, Fanyi Wang, Cheng Li, Chenyang Yang, Kaituo Liu, Bei Boon, Chirn Chye A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology |
| title | A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology |
| title_full | A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology |
| title_fullStr | A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology |
| title_full_unstemmed | A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology |
| title_short | A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology |
| title_sort | 93 4 104 8 ghz 57 mw fractional n cascaded pll with true in phase injection coupled qvco in 65 nm cmos technology |
| topic | Engineering::Electrical and electronic engineering Cascaded Phase-locked Loop (PLL) Frequency Synthesizer |
| url | https://hdl.handle.net/10356/144845 |
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