A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS
This paper presents an extremely low-voltage and low-power single-phase-clocking redundant-transition-free flip-flop (FF), named change-sensing FF (CSFF). By utilizing a local change-sensing scheme for eliminating redundant transitions of internal clocked nodes, CSFF does not consume any dynamic pow...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2020
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/145239 |
| _version_ | 1826110423802314752 |
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| author | Le, Van Loi Li, Juhui Chang, Alan Kim, Tony Tae-Hyoung |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Le, Van Loi Li, Juhui Chang, Alan Kim, Tony Tae-Hyoung |
| author_sort | Le, Van Loi |
| collection | NTU |
| description | This paper presents an extremely low-voltage and low-power single-phase-clocking redundant-transition-free flip-flop (FF), named change-sensing FF (CSFF). By utilizing a local change-sensing scheme for eliminating redundant transitions of internal clocked nodes, CSFF does not consume any dynamic power when there is no data activity. Measurement results from a test chip fabricated in 40-nm CMOS technology show that CSFF saves up to 90% power dissipation at 5% data activity without additional transistors compared to the conventional transmission-gate FF (TGFF). CSFF consumes only 0.138 fJ/cycle, which is 84% lower than that of TGFF, at 0.4 V and 10% activity. In addition to the significant improvement in power and energy efficiencies, CSFF also enhances performance and minimum operating voltage. The test chip measurement demonstrates successful operations of CSFF down to 0.19 V and the delay improvement of 37% compared to TGFF in the supply voltage range of 0.4-1 V. |
| first_indexed | 2024-10-01T02:34:11Z |
| format | Journal Article |
| id | ntu-10356/145239 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:34:11Z |
| publishDate | 2020 |
| record_format | dspace |
| spelling | ntu-10356/1452392020-12-15T07:44:14Z A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS Le, Van Loi Li, Juhui Chang, Alan Kim, Tony Tae-Hyoung School of Electrical and Electronic Engineering Engineering::Electrical and electronic engineering Latches Transistors This paper presents an extremely low-voltage and low-power single-phase-clocking redundant-transition-free flip-flop (FF), named change-sensing FF (CSFF). By utilizing a local change-sensing scheme for eliminating redundant transitions of internal clocked nodes, CSFF does not consume any dynamic power when there is no data activity. Measurement results from a test chip fabricated in 40-nm CMOS technology show that CSFF saves up to 90% power dissipation at 5% data activity without additional transistors compared to the conventional transmission-gate FF (TGFF). CSFF consumes only 0.138 fJ/cycle, which is 84% lower than that of TGFF, at 0.4 V and 10% activity. In addition to the significant improvement in power and energy efficiencies, CSFF also enhances performance and minimum operating voltage. The test chip measurement demonstrates successful operations of CSFF down to 0.19 V and the delay improvement of 37% compared to TGFF in the supply voltage range of 0.4-1 V. 2020-12-15T07:43:13Z 2020-12-15T07:43:13Z 2018 Journal Article Le, V. L., Li, J., Chang, A., & Kim, T. T.-H. (2018). A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS. 1558-173X https://hdl.handle.net/10356/145239 10.1109/JSSC.2018.2863946 10 53 2806 2817 en IEEE Journal of Solid-State Circuits © 2018 Institute of Electrical and Electronics Engineers (IEEE). All rights reserved. |
| spellingShingle | Engineering::Electrical and electronic engineering Latches Transistors Le, Van Loi Li, Juhui Chang, Alan Kim, Tony Tae-Hyoung A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS |
| title | A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS |
| title_full | A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS |
| title_fullStr | A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS |
| title_full_unstemmed | A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS |
| title_short | A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS |
| title_sort | 0 4 v 0 138 fj cycle single phase clocking redundant transition free 24t flip flop with change sensing scheme in 40 nm cmos |
| topic | Engineering::Electrical and electronic engineering Latches Transistors |
| url | https://hdl.handle.net/10356/145239 |
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