A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS

A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS

This paper presents an extremely low-voltage and low-power single-phase-clocking redundant-transition-free flip-flop (FF), named change-sensing FF (CSFF). By utilizing a local change-sensing scheme for eliminating redundant transitions of internal clocked nodes, CSFF does not consume any dynamic pow...

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Bibliographic Details
Main Authors: Le, Van Loi, Li, Juhui, Chang, Alan, Kim, Tony Tae-Hyoung
Other Authors: School of Electrical and Electronic Engineering
Format: Journal Article
Language:English
Published: 2020
Subjects:
Engineering::Electrical and electronic engineering
Latches
Transistors
Online Access:https://hdl.handle.net/10356/145239

Internet

https://hdl.handle.net/10356/145239

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