Fast and cycle-accurate simulation of RTL NoC designs using test-driven cellular automata
Speeding up the register-transfer level (RTL) simulation of network-on-chip (NoC) is essential for design optimization under various use scenarios and parameters. One of the promising approaches for RTL NoC speedup is high-level modeling. Conventional high-level modeling approaches lead to an accura...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2021
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/145879 |