Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks
Fault injection-based cryptanalysis is one of the most powerful practical threats to modern cryptographic primitives. Popular countermeasures to such fault-based attacks generally use some formof redundant computation to detect and react/correct the injected faults. However, such countermeasures are...
| Main Authors: | , , , , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2021
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/147421 |
| _version_ | 1826128870114328576 |
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| author | Alam, Manaar Bag, Arnab Roy, Debapriya Basu Jap, Dirmanto Breier, Jakub Bhasin, Shivam Mukhopadhyay, Debdeep |
| author2 | Temasek Laboratories @ NTU |
| author_facet | Temasek Laboratories @ NTU Alam, Manaar Bag, Arnab Roy, Debapriya Basu Jap, Dirmanto Breier, Jakub Bhasin, Shivam Mukhopadhyay, Debdeep |
| author_sort | Alam, Manaar |
| collection | NTU |
| description | Fault injection-based cryptanalysis is one of the most powerful practical threats to modern cryptographic primitives. Popular countermeasures to such fault-based attacks generally use some formof redundant computation to detect and react/correct the injected faults. However, such countermeasures are shown to be vulnerable to selective fault injections. In this article, we aim to develop acryptographic primitive that is fault tolerant by its construction and does not require to compute the same value multiple times. We utilize the effectiveness of Neural Networks (NNs), which show "some degree"of robustness by functioning correctly even after the occurrence of faults inany of its parameters. We also propose a novel strategy that enhances the fault tolerance of the implementation to "high degree"(close to 100%) by incorporating selective constraints in the NN parameters during the training phase. We evaluated the performance of revised NN considering both software and FPGA implementations for standard cryptographic primitives like 8×8 AES SBox and 4×4 PRESENT SBox. The results show that the fault tolerance of such implementations canbe significantly increased with the proposed methodology. Such NN-based cryptographic primitives will provide inherent resistance against fault injections without requiring any redundancy countermeasures. |
| first_indexed | 2024-10-01T07:31:36Z |
| format | Journal Article |
| id | ntu-10356/147421 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:31:36Z |
| publishDate | 2021 |
| record_format | dspace |
| spelling | ntu-10356/1474212021-04-07T07:28:07Z Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks Alam, Manaar Bag, Arnab Roy, Debapriya Basu Jap, Dirmanto Breier, Jakub Bhasin, Shivam Mukhopadhyay, Debdeep Temasek Laboratories @ NTU Engineering::Computer science and engineering Machine Learning Hardware Security Fault injection-based cryptanalysis is one of the most powerful practical threats to modern cryptographic primitives. Popular countermeasures to such fault-based attacks generally use some formof redundant computation to detect and react/correct the injected faults. However, such countermeasures are shown to be vulnerable to selective fault injections. In this article, we aim to develop acryptographic primitive that is fault tolerant by its construction and does not require to compute the same value multiple times. We utilize the effectiveness of Neural Networks (NNs), which show "some degree"of robustness by functioning correctly even after the occurrence of faults inany of its parameters. We also propose a novel strategy that enhances the fault tolerance of the implementation to "high degree"(close to 100%) by incorporating selective constraints in the NN parameters during the training phase. We evaluated the performance of revised NN considering both software and FPGA implementations for standard cryptographic primitives like 8×8 AES SBox and 4×4 PRESENT SBox. The results show that the fault tolerance of such implementations canbe significantly increased with the proposed methodology. Such NN-based cryptographic primitives will provide inherent resistance against fault injections without requiring any redundancy countermeasures. 2021-04-07T07:28:07Z 2021-04-07T07:28:07Z 2020 Journal Article Alam, M., Bag, A., Roy, D. B., Jap, D., Breier, J., Bhasin, S. & Mukhopadhyay, D. (2020). Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks. ACM Journal On Emerging Technologies in Computing Systems, 17(1), 1-30. https://dx.doi.org/10.1145/3409594 1550-4840 https://hdl.handle.net/10356/147421 10.1145/3409594 2-s2.0-85099393355 1 17 1 30 en ACM Journal on Emerging Technologies in Computing Systems © 2020 Association for Computing Machinery (ACM). All rights reserved. |
| spellingShingle | Engineering::Computer science and engineering Machine Learning Hardware Security Alam, Manaar Bag, Arnab Roy, Debapriya Basu Jap, Dirmanto Breier, Jakub Bhasin, Shivam Mukhopadhyay, Debdeep Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks |
| title | Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks |
| title_full | Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks |
| title_fullStr | Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks |
| title_full_unstemmed | Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks |
| title_short | Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks |
| title_sort | neural network based inherently fault tolerant hardware cryptographic primitives without explicit redundancy checks |
| topic | Engineering::Computer science and engineering Machine Learning Hardware Security |
| url | https://hdl.handle.net/10356/147421 |
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