Lowering dynamic power of a stream-based CNN hardware accelerator
Custom hardware accelerators of Convolutional Neural Networks (CNN) provide a promising solution to meet real-time constraints for a wide range of applications on low-cost embedded devices. In this work, we aim to lower the dynamic power of a stream-based CNN hardware accelerator by reducing the com...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2021
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/147509 |
| _version_ | 1826117392073228288 |
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| author | Piyasena, Duvindu Wickramasinghe, Rukshan Paul, Debdeep Lam, Siew-Kei Wu, Meiqing |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Piyasena, Duvindu Wickramasinghe, Rukshan Paul, Debdeep Lam, Siew-Kei Wu, Meiqing |
| author_sort | Piyasena, Duvindu |
| collection | NTU |
| description | Custom hardware accelerators of Convolutional Neural Networks (CNN) provide a promising solution to meet real-time constraints for a wide range of applications on low-cost embedded devices. In this work, we aim to lower the dynamic power of a stream-based CNN hardware accelerator by reducing the computational redundancies in the CNN layers. In particular, we investigate the redundancies due to the downsampling effect of max pooling layers which are prevalent in state-of-the-art CNNs, and propose an approximation method to reduce the overall computations. The experimental results show that the proposed method leads to lower dynamic power without sacrificing accuracy. |
| first_indexed | 2024-10-01T04:26:31Z |
| format | Conference Paper |
| id | ntu-10356/147509 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:26:31Z |
| publishDate | 2021 |
| record_format | dspace |
| spelling | ntu-10356/1475092021-04-19T03:27:20Z Lowering dynamic power of a stream-based CNN hardware accelerator Piyasena, Duvindu Wickramasinghe, Rukshan Paul, Debdeep Lam, Siew-Kei Wu, Meiqing School of Computer Science and Engineering 2019 IEEE 21st International Workshop on Multimedia Signal Processing (MMSP) Hardware & Embedded Systems Lab (HESL) Engineering::Computer science and engineering::Hardware::Register-transfer-level implementation Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision FPGA Convolutional Neural Networks Custom hardware accelerators of Convolutional Neural Networks (CNN) provide a promising solution to meet real-time constraints for a wide range of applications on low-cost embedded devices. In this work, we aim to lower the dynamic power of a stream-based CNN hardware accelerator by reducing the computational redundancies in the CNN layers. In particular, we investigate the redundancies due to the downsampling effect of max pooling layers which are prevalent in state-of-the-art CNNs, and propose an approximation method to reduce the overall computations. The experimental results show that the proposed method leads to lower dynamic power without sacrificing accuracy. National Research Foundation (NRF) Accepted version This research project is funded by the National Research Foundation Singapore under its Campus for Research Excellence and Technological Enterprise (CREATE) programme with the Technical University of Munich at TUMCREATE. 2021-04-19T03:27:20Z 2021-04-19T03:27:20Z 2019 Conference Paper Piyasena, D., Wickramasinghe, R., Paul, D., Lam, S. & Wu, M. (2019). Lowering dynamic power of a stream-based CNN hardware accelerator. 2019 IEEE 21st International Workshop on Multimedia Signal Processing (MMSP), 1-6. https://dx.doi.org/10.1109/MMSP.2019.8901777 9781728118178 https://hdl.handle.net/10356/147509 10.1109/MMSP.2019.8901777 2-s2.0-85075739729 1 6 en TUM CREATE © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/MMSP.2019.8901777 application/pdf |
| spellingShingle | Engineering::Computer science and engineering::Hardware::Register-transfer-level implementation Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision FPGA Convolutional Neural Networks Piyasena, Duvindu Wickramasinghe, Rukshan Paul, Debdeep Lam, Siew-Kei Wu, Meiqing Lowering dynamic power of a stream-based CNN hardware accelerator |
| title | Lowering dynamic power of a stream-based CNN hardware accelerator |
| title_full | Lowering dynamic power of a stream-based CNN hardware accelerator |
| title_fullStr | Lowering dynamic power of a stream-based CNN hardware accelerator |
| title_full_unstemmed | Lowering dynamic power of a stream-based CNN hardware accelerator |
| title_short | Lowering dynamic power of a stream-based CNN hardware accelerator |
| title_sort | lowering dynamic power of a stream based cnn hardware accelerator |
| topic | Engineering::Computer science and engineering::Hardware::Register-transfer-level implementation Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision FPGA Convolutional Neural Networks |
| url | https://hdl.handle.net/10356/147509 |
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