Design a 16-bit low power delay multiplier
In this paper, a low power delay multiplier design is proposed. Aiming to achieve high performance, improvements has been done both in algorithm and architecture level. In algorithm level, a radix 4 modified Booth’s algorithm is applied to reduce the partial products for one half. And in the archite...
| Hovedforfatter: | |
|---|---|
| Andre forfattere: | |
| Format: | Thesis-Master by Coursework |
| Sprog: | English |
| Udgivet: |
Nanyang Technological University
2021
|
| Fag: | |
| Online adgang: | https://hdl.handle.net/10356/150272 |