Design a 16-bit low power delay multiplier
In this paper, a low power delay multiplier design is proposed. Aiming to achieve high performance, improvements has been done both in algorithm and architecture level. In algorithm level, a radix 4 modified Booth’s algorithm is applied to reduce the partial products for one half. And in the archite...
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| Materyal Türü: | Thesis-Master by Coursework |
| Dil: | English |
| Baskı/Yayın Bilgisi: |
Nanyang Technological University
2021
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| Online Erişim: | https://hdl.handle.net/10356/150272 |