Dual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES : design, countermeasures and evaluation

Dual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES : design, countermeasures and evaluation

We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and the time moderation (horizontal dimension). There are five contributions in t...

Повний опис

Бібліографічні деталі
Автори: Chong, Kwen-Siong, Ng, Jun-Sheng, Chen, Juncheng, Lwin, Ne Kyaw Zwa, Kyaw, Nay Aung, Ho, Weng-Geng, Chang, Joseph, Gwee, Bah-Hwee
Інші автори: School of Electrical and Electronic Engineering
Формат: Journal Article
Мова:English
Опубліковано: 2021
Предмети:
Engineering::Computer science and engineering::Hardware
Advanced Encryption Standard (AES)
Asynchronous Circuits
Онлайн доступ:https://hdl.handle.net/10356/151198

Інтернет

https://hdl.handle.net/10356/151198

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