Area-time efficient two-dimensional reconfigurable integer DCT architecture for HEVC
In this paper, we present area-time efficient reconfigurable architectures for the implementation of the integer discrete cosine transform (DCT), which supports all the transform lengths to be used in High Efficiency Video Coding (HEVC). We propose three 1D reconfigurable architectures that can be c...
| Hoofdauteurs: | , , , , |
|---|---|
| Andere auteurs: | |
| Formaat: | Journal Article |
| Taal: | English |
| Gepubliceerd in: |
2021
|
| Onderwerpen: | |
| Online toegang: | https://hdl.handle.net/10356/151887 |
| _version_ | 1826126336629932032 |
|---|---|
| author | Meher, Pramod Kumar Lam, Siew-Kei Srikanthan, Thambipillai Kim, Dong Hwan Park, Sang Yoon |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Meher, Pramod Kumar Lam, Siew-Kei Srikanthan, Thambipillai Kim, Dong Hwan Park, Sang Yoon |
| author_sort | Meher, Pramod Kumar |
| collection | NTU |
| description | In this paper, we present area-time efficient reconfigurable architectures for the implementation of the integer discrete cosine transform (DCT), which supports all the transform lengths to be used in High Efficiency Video Coding (HEVC). We propose three 1D reconfigurable architectures that can be configured for the computation of the DCT of any of the prescribed lengths such as 4, 8, 16, and 32. It is shown that matrix multiplication schemes involving fewer adders can be used to derive parallel architectures for 1D integer DCT of different lengths. A novel transposition buffer is designed to be used for the proposed 2D DCT architecture, which offers double the throughput without increasing the size of the transposition buffer. We determine the optimal pipeline locations in the proposed design through the precise estimation of propagation delays and the critical path so that the area-delay-product is optimized and all the output samples are obtained in the same cycle in spite of the recursive nature of the structure. Implementation results show that the proposed 2D integer DCT architectures provide significantly higher throughput per unit area than the existing designs for HEVC. |
| first_indexed | 2024-10-01T06:51:03Z |
| format | Journal Article |
| id | ntu-10356/151887 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:51:03Z |
| publishDate | 2021 |
| record_format | dspace |
| spelling | ntu-10356/1518872021-10-20T08:08:28Z Area-time efficient two-dimensional reconfigurable integer DCT architecture for HEVC Meher, Pramod Kumar Lam, Siew-Kei Srikanthan, Thambipillai Kim, Dong Hwan Park, Sang Yoon School of Computer Science and Engineering Engineering::Computer science and engineering Discrete Cosine Transform High Efficiency Video Coding In this paper, we present area-time efficient reconfigurable architectures for the implementation of the integer discrete cosine transform (DCT), which supports all the transform lengths to be used in High Efficiency Video Coding (HEVC). We propose three 1D reconfigurable architectures that can be configured for the computation of the DCT of any of the prescribed lengths such as 4, 8, 16, and 32. It is shown that matrix multiplication schemes involving fewer adders can be used to derive parallel architectures for 1D integer DCT of different lengths. A novel transposition buffer is designed to be used for the proposed 2D DCT architecture, which offers double the throughput without increasing the size of the transposition buffer. We determine the optimal pipeline locations in the proposed design through the precise estimation of propagation delays and the critical path so that the area-delay-product is optimized and all the output samples are obtained in the same cycle in spite of the recursive nature of the structure. Implementation results show that the proposed 2D integer DCT architectures provide significantly higher throughput per unit area than the existing designs for HEVC. Published version This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1F1A1060820). 2021-10-20T08:08:28Z 2021-10-20T08:08:28Z 2021 Journal Article Meher, P. K., Lam, S., Srikanthan, T., Kim, D. H. & Park, S. Y. (2021). Area-time efficient two-dimensional reconfigurable integer DCT architecture for HEVC. Electronics, 10(5), 603-. https://dx.doi.org/10.3390/electronics10050603 2079-9292 https://hdl.handle.net/10356/151887 10.3390/electronics10050603 2-s2.0-85102071805 5 10 603 en Electronics © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). application/pdf |
| spellingShingle | Engineering::Computer science and engineering Discrete Cosine Transform High Efficiency Video Coding Meher, Pramod Kumar Lam, Siew-Kei Srikanthan, Thambipillai Kim, Dong Hwan Park, Sang Yoon Area-time efficient two-dimensional reconfigurable integer DCT architecture for HEVC |
| title | Area-time efficient two-dimensional reconfigurable integer DCT architecture for HEVC |
| title_full | Area-time efficient two-dimensional reconfigurable integer DCT architecture for HEVC |
| title_fullStr | Area-time efficient two-dimensional reconfigurable integer DCT architecture for HEVC |
| title_full_unstemmed | Area-time efficient two-dimensional reconfigurable integer DCT architecture for HEVC |
| title_short | Area-time efficient two-dimensional reconfigurable integer DCT architecture for HEVC |
| title_sort | area time efficient two dimensional reconfigurable integer dct architecture for hevc |
| topic | Engineering::Computer science and engineering Discrete Cosine Transform High Efficiency Video Coding |
| url | https://hdl.handle.net/10356/151887 |
| work_keys_str_mv | AT meherpramodkumar areatimeefficienttwodimensionalreconfigurableintegerdctarchitectureforhevc AT lamsiewkei areatimeefficienttwodimensionalreconfigurableintegerdctarchitectureforhevc AT srikanthanthambipillai areatimeefficienttwodimensionalreconfigurableintegerdctarchitectureforhevc AT kimdonghwan areatimeefficienttwodimensionalreconfigurableintegerdctarchitectureforhevc AT parksangyoon areatimeefficienttwodimensionalreconfigurableintegerdctarchitectureforhevc |