A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS
A new vernier delay line time-to-digital converter (TDC) capable of achieving an ultra-fine resolution at an ultra-low supply voltage is designed in 180 nm / 1.8 V CMOS process. The proposed TDC named as capacitively boosted vernier delay line TDC (CB-VDL TDC) consists of a vernier delay line built...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2021
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| Online Access: | https://hdl.handle.net/10356/152105 |
| _version_ | 1811687224711839744 |
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| author | Palaniappan, Arjun Ramaswami Siek, Liter |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Palaniappan, Arjun Ramaswami Siek, Liter |
| author_sort | Palaniappan, Arjun Ramaswami |
| collection | NTU |
| description | A new vernier delay line time-to-digital converter (TDC) capable of achieving an ultra-fine resolution at an ultra-low supply voltage is designed in 180 nm / 1.8 V CMOS process. The proposed TDC named as capacitively boosted vernier delay line TDC (CB-VDL TDC) consists of a vernier delay line built using capacitive boosting delay buffers capable of amplifying the input time signals higher than the supply and below the ground for driving the subsequent buffers with improved strength even at an ultra-low operating supply voltage. The proposed 6-bit CB-VDL TDC achieves an ultra-fine resolution of 1.74 ps while operating at an ultra-low supply of 0.6 V and consumes a power of 217.43 μW at a sampling frequency of 50 MHz, thus making it highly suitable for applications such as low power all-digital phase locked loops, time-of-flight measurement systems and time-mode analog-to-digital converters. The TDC core occupies an area of 1.225 mm 2 including the on-chip calibration unit in 180 nm CMOS. |
| first_indexed | 2024-10-01T05:12:55Z |
| format | Conference Paper |
| id | ntu-10356/152105 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:12:55Z |
| publishDate | 2021 |
| record_format | dspace |
| spelling | ntu-10356/1521052021-07-16T06:43:07Z A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS Palaniappan, Arjun Ramaswami Siek, Liter School of Electrical and Electronic Engineering 2019 IEEE International Symposium on Circuits and Systems (ISCAS) NXP EDB A*STAR NTU VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering Time-To-Digital Converter (TDC) Vernier Delay Line A new vernier delay line time-to-digital converter (TDC) capable of achieving an ultra-fine resolution at an ultra-low supply voltage is designed in 180 nm / 1.8 V CMOS process. The proposed TDC named as capacitively boosted vernier delay line TDC (CB-VDL TDC) consists of a vernier delay line built using capacitive boosting delay buffers capable of amplifying the input time signals higher than the supply and below the ground for driving the subsequent buffers with improved strength even at an ultra-low operating supply voltage. The proposed 6-bit CB-VDL TDC achieves an ultra-fine resolution of 1.74 ps while operating at an ultra-low supply of 0.6 V and consumes a power of 217.43 μW at a sampling frequency of 50 MHz, thus making it highly suitable for applications such as low power all-digital phase locked loops, time-of-flight measurement systems and time-mode analog-to-digital converters. The TDC core occupies an area of 1.225 mm 2 including the on-chip calibration unit in 180 nm CMOS. Agency for Science, Technology and Research (A*STAR) Economic Development Board (EDB) Nanyang Technological University The authors would like to acknowledge the JIP scholarship support from EDB, Singapore and NXP Semiconductors, Singapore. The authors also acknowledge the tape-out funding support from NTU-A*STAR Silicon Technologies Centre of Excellence under the program grant No. 11235100003. 2021-07-16T06:24:08Z 2021-07-16T06:24:08Z 2019 Conference Paper Palaniappan, A. R. & Siek, L. (2019). A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS. 2019 IEEE International Symposium on Circuits and Systems (ISCAS). https://dx.doi.org/10.1109/ISCAS.2019.8702624 978-1-7281-0397-6 2158-1525 https://hdl.handle.net/10356/152105 10.1109/ISCAS.2019.8702624 en © 2019 Institute of Electrical and Electronics Engineers (IEEE). All rights reserved. |
| spellingShingle | Engineering::Electrical and electronic engineering Time-To-Digital Converter (TDC) Vernier Delay Line Palaniappan, Arjun Ramaswami Siek, Liter A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS |
| title | A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS |
| title_full | A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS |
| title_fullStr | A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS |
| title_full_unstemmed | A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS |
| title_short | A 0.6 V, 1.74 ps resolution capacitively boosted time-to-digital converter in 180 nm CMOS |
| title_sort | 0 6 v 1 74 ps resolution capacitively boosted time to digital converter in 180 nm cmos |
| topic | Engineering::Electrical and electronic engineering Time-To-Digital Converter (TDC) Vernier Delay Line |
| url | https://hdl.handle.net/10356/152105 |
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