A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS
As technology advances, digital circuits are reaping the benefits more than its analog counterpart. Time-to-Digital converters (TDC) are aiding the transition of some traditionally analog circuits into the digital domain. In this paper, a 14-bits fully synthesizable stochastic-based branching TDC is...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2021
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/152114 |
| _version_ | 1811677766365478912 |
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| author | Teh, Jian Sen Siek, Liter Alonso, Abdel Martinez Firdauzi, Anugerah Matsuzawa, Akira |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Teh, Jian Sen Siek, Liter Alonso, Abdel Martinez Firdauzi, Anugerah Matsuzawa, Akira |
| author_sort | Teh, Jian Sen |
| collection | NTU |
| description | As technology advances, digital circuits are reaping the benefits more than its analog counterpart. Time-to-Digital converters (TDC) are aiding the transition of some traditionally analog circuits into the digital domain. In this paper, a 14-bits fully synthesizable stochastic-based branching TDC is proposed. As compared to prior work, it has its own oscillation source on-chip. Moreover, it has a coarse-fine architecture with a smooth coarse-fine interface that allows it to extend its range easily without incurring large overhead costs. It was synthesized in a standard 65nm/1.2V CMOS technology using a VDD of 0.8 V. It is expected to achieve a resolution of 850fs. Simulation results shows a DNL & INL of 0.27 & 2.94LSB respectively, with a FoM of 136/J/conv. step. At a sampling rate of 125MS/s, it consumes 70.8mWof power. |
| first_indexed | 2024-10-01T02:42:35Z |
| format | Conference Paper |
| id | ntu-10356/152114 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:42:35Z |
| publishDate | 2021 |
| record_format | dspace |
| spelling | ntu-10356/1521142021-07-21T01:52:37Z A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS Teh, Jian Sen Siek, Liter Alonso, Abdel Martinez Firdauzi, Anugerah Matsuzawa, Akira School of Electrical and Electronic Engineering 2018 IEEE International Symposium on Circuits and Systems (ISCAS) MediaTek Tokyo Institute of Technology VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering Time-to-Digital Converter (TDC) Branching As technology advances, digital circuits are reaping the benefits more than its analog counterpart. Time-to-Digital converters (TDC) are aiding the transition of some traditionally analog circuits into the digital domain. In this paper, a 14-bits fully synthesizable stochastic-based branching TDC is proposed. As compared to prior work, it has its own oscillation source on-chip. Moreover, it has a coarse-fine architecture with a smooth coarse-fine interface that allows it to extend its range easily without incurring large overhead costs. It was synthesized in a standard 65nm/1.2V CMOS technology using a VDD of 0.8 V. It is expected to achieve a resolution of 850fs. Simulation results shows a DNL & INL of 0.27 & 2.94LSB respectively, with a FoM of 136/J/conv. step. At a sampling rate of 125MS/s, it consumes 70.8mWof power. We would like to thank MediaTek for funding the chip fabrication. 2021-07-21T01:52:36Z 2021-07-21T01:52:36Z 2018 Conference Paper Teh, J. S., Siek, L., Alonso, A. M., Firdauzi, A. & Matsuzawa, A. (2018). A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS. 2018 IEEE International Symposium on Circuits and Systems (ISCAS). https://dx.doi.org/10.1109/ISCAS.2018.8350981 978-1-5386-4882-7 2379-447X https://hdl.handle.net/10356/152114 10.1109/ISCAS.2018.8350981 en © 2018 Institute of Electrical and Electronics Engineers (IEEE). All rights reserved. |
| spellingShingle | Engineering::Electrical and electronic engineering Time-to-Digital Converter (TDC) Branching Teh, Jian Sen Siek, Liter Alonso, Abdel Martinez Firdauzi, Anugerah Matsuzawa, Akira A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS |
| title | A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS |
| title_full | A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS |
| title_fullStr | A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS |
| title_full_unstemmed | A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS |
| title_short | A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS |
| title_sort | 14 b 850fs fully synthesizable stochastic based branching time to digital converter in 65nm cmos |
| topic | Engineering::Electrical and electronic engineering Time-to-Digital Converter (TDC) Branching |
| url | https://hdl.handle.net/10356/152114 |
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