Novel edge comparator with input time hysteresis for improved edges arbitration
Accurate edge arbitration between two input edges using arbiters or edge comparators is essential in the operation of various mixed-signal systems. However, unlike voltage comparators, input time hysteresis is difficult to be designed into edge comparators. This paper presents a novel edge comparato...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2021
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/152116 |
| _version_ | 1826117216578306048 |
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| author | Teh, Jian Sen Siek, Liter |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Teh, Jian Sen Siek, Liter |
| author_sort | Teh, Jian Sen |
| collection | NTU |
| description | Accurate edge arbitration between two input edges using arbiters or edge comparators is essential in the operation of various mixed-signal systems. However, unlike voltage comparators, input time hysteresis is difficult to be designed into edge comparators. This paper presents a novel edge comparator that has input time hysteresis effect, allowing it to be more robust against noise and jitter in repeated measurements. This was achieved using the SR latch memory effect, and two additional NMOS connected in a negative feedback manner. The proposed edge comparator was fabricated in a standard 0.18μm/1.8V CMOS technology. Simulation results shows a hysteresis window of 55fs. The SR latch memory effect and the presence of the input time hysteresis effect was verified by chip measurement. |
| first_indexed | 2024-10-01T04:24:00Z |
| format | Conference Paper |
| id | ntu-10356/152116 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:24:00Z |
| publishDate | 2021 |
| record_format | dspace |
| spelling | ntu-10356/1521162021-07-21T03:12:40Z Novel edge comparator with input time hysteresis for improved edges arbitration Teh, Jian Sen Siek, Liter School of Electrical and Electronic Engineering 2018 IEEE International Symposium on Circuits and Systems (ISCAS) A*STAR VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering Arbiters Edge Comparator Accurate edge arbitration between two input edges using arbiters or edge comparators is essential in the operation of various mixed-signal systems. However, unlike voltage comparators, input time hysteresis is difficult to be designed into edge comparators. This paper presents a novel edge comparator that has input time hysteresis effect, allowing it to be more robust against noise and jitter in repeated measurements. This was achieved using the SR latch memory effect, and two additional NMOS connected in a negative feedback manner. The proposed edge comparator was fabricated in a standard 0.18μm/1.8V CMOS technology. Simulation results shows a hysteresis window of 55fs. The SR latch memory effect and the presence of the input time hysteresis effect was verified by chip measurement. The authors would like to thank NTU-A*STAR Silicon Technologies Centre of Excellence under Program 11235100003 for sponsoring this research. 2021-07-21T03:12:40Z 2021-07-21T03:12:40Z 2018 Conference Paper Teh, J. S. & Siek, L. (2018). Novel edge comparator with input time hysteresis for improved edges arbitration. 2018 IEEE International Symposium on Circuits and Systems (ISCAS). https://dx.doi.org/10.1109/ISCAS.2018.8350928 978-1-5386-4882-7 2379-447X https://hdl.handle.net/10356/152116 10.1109/ISCAS.2018.8350928 en © 2018 Institute of Electrical and Electronics Engineers (IEEE). All rights reserved. |
| spellingShingle | Engineering::Electrical and electronic engineering Arbiters Edge Comparator Teh, Jian Sen Siek, Liter Novel edge comparator with input time hysteresis for improved edges arbitration |
| title | Novel edge comparator with input time hysteresis for improved edges arbitration |
| title_full | Novel edge comparator with input time hysteresis for improved edges arbitration |
| title_fullStr | Novel edge comparator with input time hysteresis for improved edges arbitration |
| title_full_unstemmed | Novel edge comparator with input time hysteresis for improved edges arbitration |
| title_short | Novel edge comparator with input time hysteresis for improved edges arbitration |
| title_sort | novel edge comparator with input time hysteresis for improved edges arbitration |
| topic | Engineering::Electrical and electronic engineering Arbiters Edge Comparator |
| url | https://hdl.handle.net/10356/152116 |
| work_keys_str_mv | AT tehjiansen noveledgecomparatorwithinputtimehysteresisforimprovededgesarbitration AT siekliter noveledgecomparatorwithinputtimehysteresisforimprovededgesarbitration |