Parallel multipath transmission for burst traffic optimization in point-to-point NoCs

Network-on-chip (NoC) is a promising solution to connect more than hundreds of processing elements (PEs). As the number of PEs increases, the high communication latency caused by the burst traffic hampers the speedup gained by computation acceleration. Although parallel multipath transmission is an...

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Main Authors: Chen, Hui, Zhang, Zihao, Chen, Peng, Zhu, Shien, Liu, Weichen
Other Authors: School of Computer Science and Engineering
Format: Conference Paper
Language:English
Published: 2021
Subjects:
Online Access:https://hdl.handle.net/10356/152657
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author Chen, Hui
Zhang, Zihao
Chen, Peng
Zhu, Shien
Liu, Weichen
author2 School of Computer Science and Engineering
author_facet School of Computer Science and Engineering
Chen, Hui
Zhang, Zihao
Chen, Peng
Zhu, Shien
Liu, Weichen
author_sort Chen, Hui
collection NTU
description Network-on-chip (NoC) is a promising solution to connect more than hundreds of processing elements (PEs). As the number of PEs increases, the high communication latency caused by the burst traffic hampers the speedup gained by computation acceleration. Although parallel multipath transmission is an effective method to reduce transmission latency, its advantages have not been fully exploited in previous works, especially for emerging point-To-point NoCs since: (1) Previous static message splitting strategy increases contentions when traffic loads are heavy, degrading NoC performance. (2) Only limited shortest paths are chosen, ignoring other possible paths without contentions. (3) The optimization of hardware that supports parallel multipath transmission is missing, resulting in additional overhead. Thus, we propose a software and hardware collaborated design to reduce latency in point-To-point NoCs through parallel multipath transmission. Specifically, we revise hardware design to support parallel multipath transmission efficiently. Moreover, we propose a reinforcement learning-based algorithm to decide when and how to split messages, and which path should be used according to traffic loads. Experiments show that our algorithm achieves a remarkable performance improvement (+12.1% to +21.0%) when compared with the state-of-The-Art dual-path algorithm. Also, our hardware decreases power and area consumption by 23.2% and 10.3% over the dual-path hardware.
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spelling ntu-10356/1526572022-03-21T09:28:56Z Parallel multipath transmission for burst traffic optimization in point-to-point NoCs Chen, Hui Zhang, Zihao Chen, Peng Zhu, Shien Liu, Weichen School of Computer Science and Engineering 2021 Great Lakes Symposium on VLSI (GLSVLSI '21) Engineering::Computer science and engineering Network-on-Chips Burst Traffic Optimization; Network-on-chip (NoC) is a promising solution to connect more than hundreds of processing elements (PEs). As the number of PEs increases, the high communication latency caused by the burst traffic hampers the speedup gained by computation acceleration. Although parallel multipath transmission is an effective method to reduce transmission latency, its advantages have not been fully exploited in previous works, especially for emerging point-To-point NoCs since: (1) Previous static message splitting strategy increases contentions when traffic loads are heavy, degrading NoC performance. (2) Only limited shortest paths are chosen, ignoring other possible paths without contentions. (3) The optimization of hardware that supports parallel multipath transmission is missing, resulting in additional overhead. Thus, we propose a software and hardware collaborated design to reduce latency in point-To-point NoCs through parallel multipath transmission. Specifically, we revise hardware design to support parallel multipath transmission efficiently. Moreover, we propose a reinforcement learning-based algorithm to decide when and how to split messages, and which path should be used according to traffic loads. Experiments show that our algorithm achieves a remarkable performance improvement (+12.1% to +21.0%) when compared with the state-of-The-Art dual-path algorithm. Also, our hardware decreases power and area consumption by 23.2% and 10.3% over the dual-path hardware. Ministry of Education (MOE) Nanyang Technological University This work is partially supported by the Ministry of Education, Singapore, under its Academic Research Fund Tier 2 (MoE2019-T2-1-071) and Tier 1 (MoE2019-T1-001-072), and Nanyang Technological University, Singapore, under its NAP (M4082282) and SUG (M4082087). 2021-09-13T01:04:51Z 2021-09-13T01:04:51Z 2021 Conference Paper Chen, H., Zhang, Z., Chen, P., Zhu, S. & Liu, W. (2021). Parallel multipath transmission for burst traffic optimization in point-to-point NoCs. 2021 Great Lakes Symposium on VLSI (GLSVLSI '21), 289-294. https://dx.doi.org/10.1145/3453688.3461521 9781450383936 https://hdl.handle.net/10356/152657 10.1145/3453688.3461521 2-s2.0-85109216117 289 294 en MoE2019-T2-1-071 MoE2019-T1-001-072 M4082282 M4082087 10.21979/N9/8NHU9V © 2021 Association for Computing Machinery. All rights reserved. This paper was published in Proceedings of 2021 Great Lakes Symposium on VLSI (GLSVLSI '21) and is made available with permission of Association for Computing Machinery. application/pdf
spellingShingle Engineering::Computer science and engineering
Network-on-Chips
Burst Traffic Optimization;
Chen, Hui
Zhang, Zihao
Chen, Peng
Zhu, Shien
Liu, Weichen
Parallel multipath transmission for burst traffic optimization in point-to-point NoCs
title Parallel multipath transmission for burst traffic optimization in point-to-point NoCs
title_full Parallel multipath transmission for burst traffic optimization in point-to-point NoCs
title_fullStr Parallel multipath transmission for burst traffic optimization in point-to-point NoCs
title_full_unstemmed Parallel multipath transmission for burst traffic optimization in point-to-point NoCs
title_short Parallel multipath transmission for burst traffic optimization in point-to-point NoCs
title_sort parallel multipath transmission for burst traffic optimization in point to point nocs
topic Engineering::Computer science and engineering
Network-on-Chips
Burst Traffic Optimization;
url https://hdl.handle.net/10356/152657
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