High throughput/gate AES hardware architectures based on datapath compression
This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and In...
| Main Authors: | , , , , , , , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2022
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/154464 |
| _version_ | 1811690657614397440 |
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| author | Ueno, Rei Homma, Naofumi Morioka, Sumio Miura, Noriyuki Matsuda, Kohei Nagata, Makoto Bhasin, Shivam Mathieu, Yves Graba, Tarik Danger, Jean-Luc |
| author2 | Nanyang Technopreneurship Center |
| author_facet | Nanyang Technopreneurship Center Ueno, Rei Homma, Naofumi Morioka, Sumio Miura, Noriyuki Matsuda, Kohei Nagata, Makoto Bhasin, Shivam Mathieu, Yves Graba, Tarik Danger, Jean-Luc |
| author_sort | Ueno, Rei |
| collection | NTU |
| description | This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts. |
| first_indexed | 2024-10-01T06:07:29Z |
| format | Journal Article |
| id | ntu-10356/154464 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:07:29Z |
| publishDate | 2022 |
| record_format | dspace |
| spelling | ntu-10356/1544642022-01-15T20:11:21Z High throughput/gate AES hardware architectures based on datapath compression Ueno, Rei Homma, Naofumi Morioka, Sumio Miura, Noriyuki Matsuda, Kohei Nagata, Makoto Bhasin, Shivam Mathieu, Yves Graba, Tarik Danger, Jean-Luc Nanyang Technopreneurship Center Research Techno Plaza Engineering::Electrical and electronic engineering Hardware Architectures Round-Based Encryption Architecture This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts. Published version This research has been supported by JSPS KAKENHI Grant No. 17H00729 and No. 19K21526, and JST PRESTO Grant No. JPMJPR18M3. 2022-01-14T05:23:35Z 2022-01-14T05:23:35Z 2019 Journal Article Ueno, R., Homma, N., Morioka, S., Miura, N., Matsuda, K., Nagata, M., Bhasin, S., Mathieu, Y., Graba, T. & Danger, J. (2019). High throughput/gate AES hardware architectures based on datapath compression. IEEE Transactions On Computers, 69(4), 534-548. https://dx.doi.org/10.1109/TC.2019.2957355 0018-9340 https://hdl.handle.net/10356/154464 10.1109/TC.2019.2957355 2-s2.0-85076273768 4 69 534 548 en IEEE Transactions on Computers © 2020 The Author(s). This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ application/pdf |
| spellingShingle | Engineering::Electrical and electronic engineering Hardware Architectures Round-Based Encryption Architecture Ueno, Rei Homma, Naofumi Morioka, Sumio Miura, Noriyuki Matsuda, Kohei Nagata, Makoto Bhasin, Shivam Mathieu, Yves Graba, Tarik Danger, Jean-Luc High throughput/gate AES hardware architectures based on datapath compression |
| title | High throughput/gate AES hardware architectures based on datapath compression |
| title_full | High throughput/gate AES hardware architectures based on datapath compression |
| title_fullStr | High throughput/gate AES hardware architectures based on datapath compression |
| title_full_unstemmed | High throughput/gate AES hardware architectures based on datapath compression |
| title_short | High throughput/gate AES hardware architectures based on datapath compression |
| title_sort | high throughput gate aes hardware architectures based on datapath compression |
| topic | Engineering::Electrical and electronic engineering Hardware Architectures Round-Based Encryption Architecture |
| url | https://hdl.handle.net/10356/154464 |
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