MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications
IoT edge devices of the past were designed primarily of sensors and a microcontroller that controlled the influx of data and the sensor operations. The microcontrollers had some pre-processing capabilities and their subsequent major task was to transmit this data to the central node where all the pr...
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| Other Authors: | |
| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2022
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| Online Access: | https://hdl.handle.net/10356/156009 |
| _version_ | 1811677994093117440 |
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| author | Shantanu, Raoke |
| author2 | Kim Tae Hyoung |
| author_facet | Kim Tae Hyoung Shantanu, Raoke |
| author_sort | Shantanu, Raoke |
| collection | NTU |
| description | IoT edge devices of the past were designed primarily of sensors and a microcontroller that controlled the influx of data and the sensor operations. The microcontrollers had some pre-processing capabilities and their subsequent major task was to transmit this data to the central node where all the processing occurred. This hierarchy is not energy efficient as most of power consumed by such a system was spent on data transmission from the edge devices to the parent node in wireless or wired medium. This increased the demand for edge devices with higher computing capabilities so the power envelope of the transmission task is minimal. More computation at the edge also decreases the dependency of the system on fewer or one central node that can stall the system if it faces an error. This work deals with implementing one of the major techniques to reduce the power consumed by an IoT node that is AI capable by integrating non-volatile memory to the L2 memory subsystem of a RISC-V core. This thesis will outline the work done in validating a taped-out chip with on-chip MRAM integrated with the L2 memory of the PULPissimo, followed by the progress done in integrating off-chip MRAM to a vanilla version of PULPissimo. |
| first_indexed | 2024-10-01T02:46:12Z |
| format | Thesis-Master by Coursework |
| id | ntu-10356/156009 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:46:12Z |
| publishDate | 2022 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1560092023-07-04T17:45:18Z MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications Shantanu, Raoke Kim Tae Hyoung Mohamed M. Sabry Aly School of Electrical and Electronic Engineering Technical University of Munich Hardware & Embedded Systems Lab (HESL) THKIM@ntu.edu.sg, msabry@ntu.edu.sg Engineering::Electrical and electronic engineering::Integrated circuits Engineering::Electrical and electronic engineering::Microelectronics IoT edge devices of the past were designed primarily of sensors and a microcontroller that controlled the influx of data and the sensor operations. The microcontrollers had some pre-processing capabilities and their subsequent major task was to transmit this data to the central node where all the processing occurred. This hierarchy is not energy efficient as most of power consumed by such a system was spent on data transmission from the edge devices to the parent node in wireless or wired medium. This increased the demand for edge devices with higher computing capabilities so the power envelope of the transmission task is minimal. More computation at the edge also decreases the dependency of the system on fewer or one central node that can stall the system if it faces an error. This work deals with implementing one of the major techniques to reduce the power consumed by an IoT node that is AI capable by integrating non-volatile memory to the L2 memory subsystem of a RISC-V core. This thesis will outline the work done in validating a taped-out chip with on-chip MRAM integrated with the L2 memory of the PULPissimo, followed by the progress done in integrating off-chip MRAM to a vanilla version of PULPissimo. Master of Science (Integrated Circuit Design) 2022-03-30T12:26:14Z 2022-03-30T12:26:14Z 2022 Thesis-Master by Coursework Shantanu, R. (2022). MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/156009 https://hdl.handle.net/10356/156009 en application/pdf Nanyang Technological University |
| spellingShingle | Engineering::Electrical and electronic engineering::Integrated circuits Engineering::Electrical and electronic engineering::Microelectronics Shantanu, Raoke MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications |
| title | MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications |
| title_full | MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications |
| title_fullStr | MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications |
| title_full_unstemmed | MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications |
| title_short | MRAM integration with L2 memory for a near threshold RISC-V core : implementing a low power IoT node for AI applications |
| title_sort | mram integration with l2 memory for a near threshold risc v core implementing a low power iot node for ai applications |
| topic | Engineering::Electrical and electronic engineering::Integrated circuits Engineering::Electrical and electronic engineering::Microelectronics |
| url | https://hdl.handle.net/10356/156009 |
| work_keys_str_mv | AT shantanuraoke mramintegrationwithl2memoryforanearthresholdriscvcoreimplementingalowpoweriotnodeforaiapplications |