Optimization of low-noise rapid data collection in TMDC semiconductor devices
The impending stagnation of scalability in silicon semiconductor transistor industry has led researchers to explore two-dimensional transition metal dichalcogenides (TMDCs). TMDCs can be exfoliated into a few atom-thick layers with unique electrical and optical properties. TMDCs have applications in...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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Nanyang Technological University
2022
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| Online Access: | https://hdl.handle.net/10356/156980 |
| _version_ | 1811695335819444224 |
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| author | Aggarwal, Saumay |
| author2 | Bent Weber |
| author_facet | Bent Weber Aggarwal, Saumay |
| author_sort | Aggarwal, Saumay |
| collection | NTU |
| description | The impending stagnation of scalability in silicon semiconductor transistor industry has led researchers to explore two-dimensional transition metal dichalcogenides (TMDCs). TMDCs can be exfoliated into a few atom-thick layers with unique electrical and optical properties. TMDCs have applications in nano-electronical and optoelectrical devices such as biosensors, field effect transistors (FETs), photodiodes, nano-wearable technology, and transparent flexible displays. There is still a large research potential of these materials to investigate their properties and new physics such as spintronics and valleytronics, hence there is a need to speed up and optimize the data collection for experimentation on such devices. To this end, we compare a specialist, self-contained electrical transport measurement instrument (Nanonis Tramea TM) to a traditional setup consisting of separate lock-ins, voltage sources, and amplifiers integrated together with LabView. The trade-off between their data collection time and noise level is compared, while verifying electrical transport properties of a MoS2 based FET device.
The study found the Nanonis Tramea system to be almost 100 times faster than a traditional lock-in setup with LabView, while maintaining a higher signal to noise ratio. This could potential cut down experimentation times from weeks to days. The peak mobility of the tri-layer MoS2 FET at room temperature is found to be 4.7 cm2 V-1 s-1, with an on/off ratio of 500:1. |
| first_indexed | 2024-10-01T07:21:50Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/156980 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:21:50Z |
| publishDate | 2022 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1569802023-02-28T23:17:26Z Optimization of low-noise rapid data collection in TMDC semiconductor devices Aggarwal, Saumay Bent Weber School of Physical and Mathematical Sciences b.weber@ntu.edu.sg Science::Physics The impending stagnation of scalability in silicon semiconductor transistor industry has led researchers to explore two-dimensional transition metal dichalcogenides (TMDCs). TMDCs can be exfoliated into a few atom-thick layers with unique electrical and optical properties. TMDCs have applications in nano-electronical and optoelectrical devices such as biosensors, field effect transistors (FETs), photodiodes, nano-wearable technology, and transparent flexible displays. There is still a large research potential of these materials to investigate their properties and new physics such as spintronics and valleytronics, hence there is a need to speed up and optimize the data collection for experimentation on such devices. To this end, we compare a specialist, self-contained electrical transport measurement instrument (Nanonis Tramea TM) to a traditional setup consisting of separate lock-ins, voltage sources, and amplifiers integrated together with LabView. The trade-off between their data collection time and noise level is compared, while verifying electrical transport properties of a MoS2 based FET device. The study found the Nanonis Tramea system to be almost 100 times faster than a traditional lock-in setup with LabView, while maintaining a higher signal to noise ratio. This could potential cut down experimentation times from weeks to days. The peak mobility of the tri-layer MoS2 FET at room temperature is found to be 4.7 cm2 V-1 s-1, with an on/off ratio of 500:1. Bachelor of Science in Applied Physics 2022-05-05T07:09:00Z 2022-05-05T07:09:00Z 2022 Final Year Project (FYP) Aggarwal, S. (2022). Optimization of low-noise rapid data collection in TMDC semiconductor devices. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/156980 https://hdl.handle.net/10356/156980 en application/pdf Nanyang Technological University |
| spellingShingle | Science::Physics Aggarwal, Saumay Optimization of low-noise rapid data collection in TMDC semiconductor devices |
| title | Optimization of low-noise rapid data collection in TMDC semiconductor devices |
| title_full | Optimization of low-noise rapid data collection in TMDC semiconductor devices |
| title_fullStr | Optimization of low-noise rapid data collection in TMDC semiconductor devices |
| title_full_unstemmed | Optimization of low-noise rapid data collection in TMDC semiconductor devices |
| title_short | Optimization of low-noise rapid data collection in TMDC semiconductor devices |
| title_sort | optimization of low noise rapid data collection in tmdc semiconductor devices |
| topic | Science::Physics |
| url | https://hdl.handle.net/10356/156980 |
| work_keys_str_mv | AT aggarwalsaumay optimizationoflownoiserapiddatacollectionintmdcsemiconductordevices |