Design implementation of an AES-256 hardware accelerator and its side-channel attack (SCA) evaluation
In this modern era, encryption is one of the commonly used protection measures to ensure data security. It can be used to protect sensitive data from being stolen and being exploited by any adversaries for harmful purposes. Any personal with authorized permission will be able to access or read the d...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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Nanyang Technological University
2022
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| Online Access: | https://hdl.handle.net/10356/157361 |
| _version_ | 1826117751103553536 |
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| author | Goh, Xing Han |
| author2 | Gwee Bah Hwee |
| author_facet | Gwee Bah Hwee Goh, Xing Han |
| author_sort | Goh, Xing Han |
| collection | NTU |
| description | In this modern era, encryption is one of the commonly used protection measures to ensure data security. It can be used to protect sensitive data from being stolen and being exploited by any adversaries for harmful purposes. Any personal with authorized permission will be able to access or read the data with their personalized key. Therefore, the data will be protected from any attacks as long as the personalized key is being kept well.
AES (Advanced Encryption Standard) is one of the commonly used encryption algorithms used in encrypting and protecting sensitive information. However, the secret key used to access to the data encrypted by AES can be potentially stolen away by any adversaries with the rise of cyber-physical-attack. Attackers can identify the encryption key by analysing the power dissipation and electromagnetic (EM) radiation during the encryption and decryption process. This attacking method is known as Side-Channel Attack (SCA) and it poses a serious threat towards our hardware security in this modern era.
In this project, the AES-256 encryption algorithm is implemented through a hardware design which utilizes a 256 bits key length in its encryption. The AES-256 hardware implementation undergoes more rounds of encryption and it requires a larger encryption key size compared to AES-128. After the hardware implementation design process, the AES-256 hardware design undergoes design simulation and synthesis process to verify the functionality of the design. Power simulation is performed on the AES-256 hardware design to obtain its power consumption and power traces during the encryption process. SCA is then launched towards the AES-256 design by utilizing its power traces to reveal the secret key. The results of SCA towards AES-256 design were evaluated and used to determine the vulnerability of AES-256 towards SCA. The results of the SCA analysis showed that the AES-256 design is still vulnerable towards SCA. |
| first_indexed | 2024-10-01T04:32:28Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/157361 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:32:28Z |
| publishDate | 2022 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1573612023-07-07T19:09:20Z Design implementation of an AES-256 hardware accelerator and its side-channel attack (SCA) evaluation Goh, Xing Han Gwee Bah Hwee School of Electrical and Electronic Engineering ebhgwee@ntu.edu.sg Engineering::Electrical and electronic engineering In this modern era, encryption is one of the commonly used protection measures to ensure data security. It can be used to protect sensitive data from being stolen and being exploited by any adversaries for harmful purposes. Any personal with authorized permission will be able to access or read the data with their personalized key. Therefore, the data will be protected from any attacks as long as the personalized key is being kept well. AES (Advanced Encryption Standard) is one of the commonly used encryption algorithms used in encrypting and protecting sensitive information. However, the secret key used to access to the data encrypted by AES can be potentially stolen away by any adversaries with the rise of cyber-physical-attack. Attackers can identify the encryption key by analysing the power dissipation and electromagnetic (EM) radiation during the encryption and decryption process. This attacking method is known as Side-Channel Attack (SCA) and it poses a serious threat towards our hardware security in this modern era. In this project, the AES-256 encryption algorithm is implemented through a hardware design which utilizes a 256 bits key length in its encryption. The AES-256 hardware implementation undergoes more rounds of encryption and it requires a larger encryption key size compared to AES-128. After the hardware implementation design process, the AES-256 hardware design undergoes design simulation and synthesis process to verify the functionality of the design. Power simulation is performed on the AES-256 hardware design to obtain its power consumption and power traces during the encryption process. SCA is then launched towards the AES-256 design by utilizing its power traces to reveal the secret key. The results of SCA towards AES-256 design were evaluated and used to determine the vulnerability of AES-256 towards SCA. The results of the SCA analysis showed that the AES-256 design is still vulnerable towards SCA. Bachelor of Engineering (Electrical and Electronic Engineering) 2022-05-12T05:32:49Z 2022-05-12T05:32:49Z 2022 Final Year Project (FYP) Goh, X. H. (2022). Design implementation of an AES-256 hardware accelerator and its side-channel attack (SCA) evaluation. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/157361 https://hdl.handle.net/10356/157361 en A2059-211 application/pdf Nanyang Technological University |
| spellingShingle | Engineering::Electrical and electronic engineering Goh, Xing Han Design implementation of an AES-256 hardware accelerator and its side-channel attack (SCA) evaluation |
| title | Design implementation of an AES-256 hardware accelerator and its side-channel attack (SCA) evaluation |
| title_full | Design implementation of an AES-256 hardware accelerator and its side-channel attack (SCA) evaluation |
| title_fullStr | Design implementation of an AES-256 hardware accelerator and its side-channel attack (SCA) evaluation |
| title_full_unstemmed | Design implementation of an AES-256 hardware accelerator and its side-channel attack (SCA) evaluation |
| title_short | Design implementation of an AES-256 hardware accelerator and its side-channel attack (SCA) evaluation |
| title_sort | design implementation of an aes 256 hardware accelerator and its side channel attack sca evaluation |
| topic | Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/157361 |
| work_keys_str_mv | AT gohxinghan designimplementationofanaes256hardwareacceleratoranditssidechannelattackscaevaluation |