Design of a FPGA-based physical unclonable function
As modern technology has advanced progressively throughout the years, things are getting increasingly digitized, for example: non-fungible tokens (NFTs) and crypto wallets. The security of these essential services and data are always at risk, where most of the time the data is stolen due to physi...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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Nanyang Technological University
2022
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| Online Access: | https://hdl.handle.net/10356/158180 |
| _version_ | 1826112198301188096 |
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| author | Ong, Andy Wei Wen |
| author2 | Chang Chip Hong |
| author_facet | Chang Chip Hong Ong, Andy Wei Wen |
| author_sort | Ong, Andy Wei Wen |
| collection | NTU |
| description | As modern technology has advanced progressively throughout the years, things are
getting increasingly digitized, for example: non-fungible tokens (NFTs) and crypto
wallets. The security of these essential services and data are always at risk, where
most of the time the data is stolen due to physical attacks. The security key used to
access such services and data are usually stored as a password in a memory on the
system. As such, hackers can obtain the security key using various tools and
methods, gaining access to the personal data.
Physical unclonable functions (PUFs) are emerging as promising hardware security
solutions to deal with such security issues. The security key for PUFs is only
generated when it is requested, therefore there is no need for a memory or storage for
the security key. Popular silicon based PUFs are the Arbiter PUF (APUF) and the
Ring Oscillator PUF (ROPUF). These PUFs use timing delays caused by
manufacturing process variations to generate chip unique challenge-response pairs
(CRPs) which act as the request (challenge) and security key (response). Due to the
uniqueness of the response to each specific device, the key is extremely difficult to
replicate even when using the same process, setup, and environment.
Field Programmable Gate Arrays (FPGAs) are programmable hardware systems
which differs from normal microprocessors used for Application Specific Integrated
Circuits (ASICs) due to the FPGA’s flexibility in handling various applications as
opposed to ASICs. However, the drawback of using FPGAs is the decrease in
efficiency.
In this project, the focus is on the design and implementation of an arbiter PUF on a
FPGA. The results are then analyzed based on the evaluation metrics for PUFs. |
| first_indexed | 2024-10-01T03:03:22Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/158180 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:03:22Z |
| publishDate | 2022 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1581802023-07-07T19:34:19Z Design of a FPGA-based physical unclonable function Ong, Andy Wei Wen Chang Chip Hong School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems Zheng Yue ECHChang@ntu.edu.sg Engineering::Electrical and electronic engineering::Integrated circuits As modern technology has advanced progressively throughout the years, things are getting increasingly digitized, for example: non-fungible tokens (NFTs) and crypto wallets. The security of these essential services and data are always at risk, where most of the time the data is stolen due to physical attacks. The security key used to access such services and data are usually stored as a password in a memory on the system. As such, hackers can obtain the security key using various tools and methods, gaining access to the personal data. Physical unclonable functions (PUFs) are emerging as promising hardware security solutions to deal with such security issues. The security key for PUFs is only generated when it is requested, therefore there is no need for a memory or storage for the security key. Popular silicon based PUFs are the Arbiter PUF (APUF) and the Ring Oscillator PUF (ROPUF). These PUFs use timing delays caused by manufacturing process variations to generate chip unique challenge-response pairs (CRPs) which act as the request (challenge) and security key (response). Due to the uniqueness of the response to each specific device, the key is extremely difficult to replicate even when using the same process, setup, and environment. Field Programmable Gate Arrays (FPGAs) are programmable hardware systems which differs from normal microprocessors used for Application Specific Integrated Circuits (ASICs) due to the FPGA’s flexibility in handling various applications as opposed to ASICs. However, the drawback of using FPGAs is the decrease in efficiency. In this project, the focus is on the design and implementation of an arbiter PUF on a FPGA. The results are then analyzed based on the evaluation metrics for PUFs. Bachelor of Engineering (Electrical and Electronic Engineering) 2022-05-27T06:13:03Z 2022-05-27T06:13:03Z 2022 Final Year Project (FYP) Ong, A. W. W. (2022). Design of a FPGA-based physical unclonable function. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/158180 https://hdl.handle.net/10356/158180 en A2033-211 application/pdf Nanyang Technological University |
| spellingShingle | Engineering::Electrical and electronic engineering::Integrated circuits Ong, Andy Wei Wen Design of a FPGA-based physical unclonable function |
| title | Design of a FPGA-based physical unclonable function |
| title_full | Design of a FPGA-based physical unclonable function |
| title_fullStr | Design of a FPGA-based physical unclonable function |
| title_full_unstemmed | Design of a FPGA-based physical unclonable function |
| title_short | Design of a FPGA-based physical unclonable function |
| title_sort | design of a fpga based physical unclonable function |
| topic | Engineering::Electrical and electronic engineering::Integrated circuits |
| url | https://hdl.handle.net/10356/158180 |
| work_keys_str_mv | AT ongandyweiwen designofafpgabasedphysicalunclonablefunction |