ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing
In this paper, we present a low-power anomaly detection integrated circuit (ADIC) based on a one-class classifier (OCC) neural network. The ADIC achieves low-power operation through a combination of (a) careful choice of algorithm for online learning and (b) approximate computing techniques to lo...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2022
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/160503 |
| _version_ | 1811683191503716352 |
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| author | Kar, Bapi Gopalakrishnan, Pradeep Kumar Bose, Sumon Kumar Roy, Mohendra Basu, Arindam |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Kar, Bapi Gopalakrishnan, Pradeep Kumar Bose, Sumon Kumar Roy, Mohendra Basu, Arindam |
| author_sort | Kar, Bapi |
| collection | NTU |
| description | In this paper, we present a low-power anomaly detection integrated circuit
(ADIC) based on a one-class classifier (OCC) neural network. The ADIC achieves
low-power operation through a combination of (a) careful choice of algorithm
for online learning and (b) approximate computing techniques to lower average
energy. In particular, online pseudoinverse update method (OPIUM) is used to
train a randomized neural network for quick and resource efficient learning. An
additional 42% energy saving can be achieved when a lighter version of OPIUM
method is used for training with the same number of data samples lead to no
significant compromise on the quality of inference. Instead of a single
classifier with large number of neurons, an ensemble of K base learner approach
is chosen to reduce learning memory by a factor of K. This also enables
approximate computing by dynamically varying the neural network size based on
anomaly detection. Fabricated in 65nm CMOS, the ADIC has K = 7 Base Learners
(BL) with 32 neurons in each BL and dissipates 11.87pJ/OP and 3.35pJ/OP during
learning and inference respectively at Vdd = 0.75V when all 7 BLs are enabled.
Further, evaluated on the NASA bearing dataset, approximately 80% of the chip
can be shut down for 99% of the lifetime leading to an energy efficiency of
0.48pJ/OP, an 18.5 times reduction over full-precision computing running at Vdd
= 1.2V throughout the lifetime. |
| first_indexed | 2024-10-01T04:08:49Z |
| format | Journal Article |
| id | ntu-10356/160503 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:08:49Z |
| publishDate | 2022 |
| record_format | dspace |
| spelling | ntu-10356/1605032022-07-25T08:26:45Z ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing Kar, Bapi Gopalakrishnan, Pradeep Kumar Bose, Sumon Kumar Roy, Mohendra Basu, Arindam School of Electrical and Electronic Engineering Delta-NTU Corporate Laboratory for Cyber Physical Systems Engineering::Electrical and electronic engineering Anomaly Detection Approximate Computing In this paper, we present a low-power anomaly detection integrated circuit (ADIC) based on a one-class classifier (OCC) neural network. The ADIC achieves low-power operation through a combination of (a) careful choice of algorithm for online learning and (b) approximate computing techniques to lower average energy. In particular, online pseudoinverse update method (OPIUM) is used to train a randomized neural network for quick and resource efficient learning. An additional 42% energy saving can be achieved when a lighter version of OPIUM method is used for training with the same number of data samples lead to no significant compromise on the quality of inference. Instead of a single classifier with large number of neurons, an ensemble of K base learner approach is chosen to reduce learning memory by a factor of K. This also enables approximate computing by dynamically varying the neural network size based on anomaly detection. Fabricated in 65nm CMOS, the ADIC has K = 7 Base Learners (BL) with 32 neurons in each BL and dissipates 11.87pJ/OP and 3.35pJ/OP during learning and inference respectively at Vdd = 0.75V when all 7 BLs are enabled. Further, evaluated on the NASA bearing dataset, approximately 80% of the chip can be shut down for 99% of the lifetime leading to an energy efficiency of 0.48pJ/OP, an 18.5 times reduction over full-precision computing running at Vdd = 1.2V throughout the lifetime. National Research Foundation (NRF) This work was supported in part by Delta Electronics Inc. and in part by the National Research Foundation Singapore under the Corporate Laboratory@UniversityScheme. 2022-07-25T08:26:45Z 2022-07-25T08:26:45Z 2020 Journal Article Kar, B., Gopalakrishnan, P. K., Bose, S. K., Roy, M. & Basu, A. (2020). ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing. IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 28(12), 2518-2529. https://dx.doi.org/10.1109/TVLSI.2020.3016939 1063-8210 https://hdl.handle.net/10356/160503 10.1109/TVLSI.2020.3016939 2-s2.0-85097353599 12 28 2518 2529 en IEEE Transactions on Very Large Scale Integration (VLSI) Systems © 2020 IEEE. All rights reserved. |
| spellingShingle | Engineering::Electrical and electronic engineering Anomaly Detection Approximate Computing Kar, Bapi Gopalakrishnan, Pradeep Kumar Bose, Sumon Kumar Roy, Mohendra Basu, Arindam ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing |
| title | ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing |
| title_full | ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing |
| title_fullStr | ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing |
| title_full_unstemmed | ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing |
| title_short | ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing |
| title_sort | adic anomaly detection integrated circuit in 65 nm cmos utilizing approximate computing |
| topic | Engineering::Electrical and electronic engineering Anomaly Detection Approximate Computing |
| url | https://hdl.handle.net/10356/160503 |
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