High-speed and energy-efficient carry look-ahead adder
The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2022
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| Online Access: | https://hdl.handle.net/10356/161227 |
| _version_ | 1811677544455340032 |
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| author | Balasubramanian, Padmanabhan Mastorakis, Nikos E. |
| author2 | School of Computer Science and Engineering |
| author_facet | School of Computer Science and Engineering Balasubramanian, Padmanabhan Mastorakis, Nikos E. |
| author_sort | Balasubramanian, Padmanabhan |
| collection | NTU |
| description | The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison. |
| first_indexed | 2024-10-01T02:39:03Z |
| format | Journal Article |
| id | ntu-10356/161227 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:39:03Z |
| publishDate | 2022 |
| record_format | dspace |
| spelling | ntu-10356/1612272022-08-22T02:16:14Z High-speed and energy-efficient carry look-ahead adder Balasubramanian, Padmanabhan Mastorakis, Nikos E. School of Computer Science and Engineering Hardware & Embedded Systems Lab (HESL) Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures Engineering::Electrical and electronic engineering::Integrated circuits Engineering::Electrical and electronic engineering::Microelectronics Engineering::Electrical and electronic engineering::Electronic circuits Arithmetic Circuits Digital Circuits VLSI Design Low Power Design Logic Design Adder The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison. Published version 2022-08-22T02:16:13Z 2022-08-22T02:16:13Z 2022 Journal Article Balasubramanian, P. & Mastorakis, N. E. (2022). High-speed and energy-efficient carry look-ahead adder. Journal of Low Power Electronics and Applications, 12(3), 46-. https://dx.doi.org/10.3390/jlpea12030046 2079-9268 https://hdl.handle.net/10356/161227 10.3390/jlpea12030046 3 12 46 en Journal of Low Power Electronics and Applications © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). application/pdf |
| spellingShingle | Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures Engineering::Electrical and electronic engineering::Integrated circuits Engineering::Electrical and electronic engineering::Microelectronics Engineering::Electrical and electronic engineering::Electronic circuits Arithmetic Circuits Digital Circuits VLSI Design Low Power Design Logic Design Adder Balasubramanian, Padmanabhan Mastorakis, Nikos E. High-speed and energy-efficient carry look-ahead adder |
| title | High-speed and energy-efficient carry look-ahead adder |
| title_full | High-speed and energy-efficient carry look-ahead adder |
| title_fullStr | High-speed and energy-efficient carry look-ahead adder |
| title_full_unstemmed | High-speed and energy-efficient carry look-ahead adder |
| title_short | High-speed and energy-efficient carry look-ahead adder |
| title_sort | high speed and energy efficient carry look ahead adder |
| topic | Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures Engineering::Electrical and electronic engineering::Integrated circuits Engineering::Electrical and electronic engineering::Microelectronics Engineering::Electrical and electronic engineering::Electronic circuits Arithmetic Circuits Digital Circuits VLSI Design Low Power Design Logic Design Adder |
| url | https://hdl.handle.net/10356/161227 |
| work_keys_str_mv | AT balasubramanianpadmanabhan highspeedandenergyefficientcarrylookaheadadder AT mastorakisnikose highspeedandenergyefficientcarrylookaheadadder |