Chip scale atomic clock for satellite timing and navigation application
Currently, with the advancement of technology, especially satellites and robots, it is easier to collect data about outer space. Having a precise and reliable time reference as the Earth is one of the most essential things in space exploration since it affects the accuracy of spacecraft positi...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
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Nanyang Technological University
2022
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/163580 |
| _version_ | 1826112005767954432 |
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| author | Pham, Quang Huy |
| author2 | Li King Ho Holden |
| author_facet | Li King Ho Holden Pham, Quang Huy |
| author_sort | Pham, Quang Huy |
| collection | NTU |
| description | Currently, with the advancement of technology, especially satellites and robots, it is
easier to collect data about outer space. Having a precise and reliable time reference as the
Earth is one of the most essential things in space exploration since it affects the accuracy of
spacecraft positioning and data mapping. The Chip Scale Atomic Clock (CSAC) is an atomic
clock using caesium with excellent short-term stability as illustrated from the Allan deviation
analysis. In space application, that amount of uncertainty in time can transfer to an error of
0.09 meters in distance and can be larger. However, being small, light, and precise, CSAC is
a potential candidate for small satellites application. Hence, it is essential to develop a
simulator for understanding and estimating the clock performance of the CSAC during a
satellite mission. In this project, the three-state model with additional aging and temperature
effect was described and applied in numerical simulations of the clock performance of CSAC.
In addition, the experiment was developed and set up to verify the errors of CSAC in one-way
ranging measurements. This project has designed and developed a fundamental experiment
setup for one-way ranging measurement and succeeded in obtaining simulation results within
the acceptable ranges from the reported data. |
| first_indexed | 2024-10-01T02:59:50Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/163580 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:59:50Z |
| publishDate | 2022 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1635802022-12-12T03:17:58Z Chip scale atomic clock for satellite timing and navigation application Pham, Quang Huy Li King Ho Holden School of Mechanical and Aerospace Engineering Chow Chee Lap HoldenLi@ntu.edu.sg, clchow@ntu.edu.sg Engineering::Mechanical engineering Currently, with the advancement of technology, especially satellites and robots, it is easier to collect data about outer space. Having a precise and reliable time reference as the Earth is one of the most essential things in space exploration since it affects the accuracy of spacecraft positioning and data mapping. The Chip Scale Atomic Clock (CSAC) is an atomic clock using caesium with excellent short-term stability as illustrated from the Allan deviation analysis. In space application, that amount of uncertainty in time can transfer to an error of 0.09 meters in distance and can be larger. However, being small, light, and precise, CSAC is a potential candidate for small satellites application. Hence, it is essential to develop a simulator for understanding and estimating the clock performance of the CSAC during a satellite mission. In this project, the three-state model with additional aging and temperature effect was described and applied in numerical simulations of the clock performance of CSAC. In addition, the experiment was developed and set up to verify the errors of CSAC in one-way ranging measurements. This project has designed and developed a fundamental experiment setup for one-way ranging measurement and succeeded in obtaining simulation results within the acceptable ranges from the reported data. Bachelor of Engineering (Aerospace Engineering) 2022-12-12T03:00:53Z 2022-12-12T03:00:53Z 2023 Final Year Project (FYP) Pham, Q. H. (2023). Chip scale atomic clock for satellite timing and navigation application. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/163580 https://hdl.handle.net/10356/163580 en B470 application/pdf Nanyang Technological University |
| spellingShingle | Engineering::Mechanical engineering Pham, Quang Huy Chip scale atomic clock for satellite timing and navigation application |
| title | Chip scale atomic clock for satellite timing and navigation application |
| title_full | Chip scale atomic clock for satellite timing and navigation application |
| title_fullStr | Chip scale atomic clock for satellite timing and navigation application |
| title_full_unstemmed | Chip scale atomic clock for satellite timing and navigation application |
| title_short | Chip scale atomic clock for satellite timing and navigation application |
| title_sort | chip scale atomic clock for satellite timing and navigation application |
| topic | Engineering::Mechanical engineering |
| url | https://hdl.handle.net/10356/163580 |
| work_keys_str_mv | AT phamquanghuy chipscaleatomicclockforsatellitetimingandnavigationapplication |