Design of a CMOS voltage reference with output voltage doubling using modified 2-transistor topology
This dissertation presents an ultra-low power CMOS voltage reference which operates in the subthreshold region. Modified from the conventional 2T circuit, the proposed circuit is capable to generate higher output voltage by using the resistor subdivision. The design comprises a negative-thresh...
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| Other Authors: | |
| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2023
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/164104 |
| _version_ | 1811687148251774976 |
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| author | Li, Junyao |
| author2 | Chan Pak Kwong |
| author_facet | Chan Pak Kwong Li, Junyao |
| author_sort | Li, Junyao |
| collection | NTU |
| description | This dissertation presents an ultra-low power CMOS voltage reference which
operates in the subthreshold region. Modified from the conventional 2T circuit,
the proposed circuit is capable to generate higher output voltage by using the
resistor subdivision. The design comprises a negative-threshold native NMOS
transistor as the current generator, a high-threshold PMOS transistor as the active
load and an active voltage doubling network to generate the reference voltage.
Implemented in TSMC 40nm CMOS technology, the proposed circuit operat es at
a minimum supply of 0.65V and consumes 5.5nA. Under one sample simulation,
the obtained T.C. is 16.64 ppm/°C and the nominal 𝑉𝑟𝑒𝑓 is 489.6mV (75.3%
of 𝑉𝑑𝑑𝑚𝑖𝑛) of for the temperature range from -20°C to 80°C. For Monte-Carlo
simulation of 200 samples at room temperature, the average output voltage is
488mV and the average T.C. is 29.6 ppm/°C whilst with the standard deviation of
13.26 ppm/°C. Finally, at room temperature, the proposed voltage reference has
achieved a process sensitivity (σ/μ) of 3.9%, a line sensitivity of 0.51%/V and a
power supply rejection of -45.5 dB and -76.3 dB at 1 Hz and 100 MHz. Compared
to the representative prior-art works realized in same technology and similar
supply current, the proposed circuit has offered the best 1-sampe T.C., the best
average T.C. in multiple samples, the highest output voltage, the maximum output
voltage per minimum supply voltage and the lowest process sensitivity in the
output, 𝑉𝑟𝑒𝑓 |
| first_indexed | 2024-10-01T05:11:42Z |
| format | Thesis-Master by Coursework |
| id | ntu-10356/164104 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:11:42Z |
| publishDate | 2023 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1641042023-07-04T17:46:53Z Design of a CMOS voltage reference with output voltage doubling using modified 2-transistor topology Li, Junyao Chan Pak Kwong School of Electrical and Electronic Engineering epkchan@ntu.edu.sg Engineering::Electrical and electronic engineering This dissertation presents an ultra-low power CMOS voltage reference which operates in the subthreshold region. Modified from the conventional 2T circuit, the proposed circuit is capable to generate higher output voltage by using the resistor subdivision. The design comprises a negative-threshold native NMOS transistor as the current generator, a high-threshold PMOS transistor as the active load and an active voltage doubling network to generate the reference voltage. Implemented in TSMC 40nm CMOS technology, the proposed circuit operat es at a minimum supply of 0.65V and consumes 5.5nA. Under one sample simulation, the obtained T.C. is 16.64 ppm/°C and the nominal 𝑉𝑟𝑒𝑓 is 489.6mV (75.3% of 𝑉𝑑𝑑𝑚𝑖𝑛) of for the temperature range from -20°C to 80°C. For Monte-Carlo simulation of 200 samples at room temperature, the average output voltage is 488mV and the average T.C. is 29.6 ppm/°C whilst with the standard deviation of 13.26 ppm/°C. Finally, at room temperature, the proposed voltage reference has achieved a process sensitivity (σ/μ) of 3.9%, a line sensitivity of 0.51%/V and a power supply rejection of -45.5 dB and -76.3 dB at 1 Hz and 100 MHz. Compared to the representative prior-art works realized in same technology and similar supply current, the proposed circuit has offered the best 1-sampe T.C., the best average T.C. in multiple samples, the highest output voltage, the maximum output voltage per minimum supply voltage and the lowest process sensitivity in the output, 𝑉𝑟𝑒𝑓 Master of Science (Electronics) 2023-01-05T02:52:18Z 2023-01-05T02:52:18Z 2022 Thesis-Master by Coursework Li, J. (2022). Design of a CMOS voltage reference with output voltage doubling using modified 2-transistor topology. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/164104 https://hdl.handle.net/10356/164104 en application/pdf Nanyang Technological University |
| spellingShingle | Engineering::Electrical and electronic engineering Li, Junyao Design of a CMOS voltage reference with output voltage doubling using modified 2-transistor topology |
| title | Design of a CMOS voltage reference with output voltage doubling using modified 2-transistor topology |
| title_full | Design of a CMOS voltage reference with output voltage doubling using modified 2-transistor topology |
| title_fullStr | Design of a CMOS voltage reference with output voltage doubling using modified 2-transistor topology |
| title_full_unstemmed | Design of a CMOS voltage reference with output voltage doubling using modified 2-transistor topology |
| title_short | Design of a CMOS voltage reference with output voltage doubling using modified 2-transistor topology |
| title_sort | design of a cmos voltage reference with output voltage doubling using modified 2 transistor topology |
| topic | Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/164104 |
| work_keys_str_mv | AT lijunyao designofacmosvoltagereferencewithoutputvoltagedoublingusingmodified2transistortopology |