High-performance CMOS digital multiplier IC design

High-performance CMOS digital multiplier IC design

A digital multiplier is a common block in processors, and its speed has a significant impact on the performance of the chip. Many new design ideas have emerged around how to improve the speed of multipliers, including pipeline structure, Wallace Tree structure, and Booth encoding. The Wallace Tree s...

Бүрэн тодорхойлолт

Номзүйн дэлгэрэнгүй
Үндсэн зохиолч:	Chu, Zhuolin
Бусад зохиолчид:	Gwee Bah Hwee
Формат:	Thesis-Master by Coursework
Хэл сонгох:	English
Хэвлэсэн:	Nanyang Technological University 2023
Нөхцлүүд:	Engineering::Electrical and electronic engineering
Онлайн хандалт:	https://hdl.handle.net/10356/164473

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