A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS
A 0.6 V voltage-to-time converter (VTC) has been presented in this work for the emerging energy-efficient time-domain circuits and systems. The proposed VTC supports a rail-to-rail input by leveraging shrink sampling with two cascaded voltage sampling and charge sharing switches, breaking the tradeo...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2023
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/165010 |
| _version_ | 1826113140266369024 |
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| author | Chen, Qian Boon, Chirn Chye Liang, Yuan |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Chen, Qian Boon, Chirn Chye Liang, Yuan |
| author_sort | Chen, Qian |
| collection | NTU |
| description | A 0.6 V voltage-to-time converter (VTC) has been presented in this work for the emerging energy-efficient time-domain circuits and systems. The proposed VTC supports a rail-to-rail input by leveraging shrink sampling with two cascaded voltage sampling and charge sharing switches, breaking the tradeoff between linearity and input range of the traditional VTC and enabling low voltage operation. The charging current source is adjustable to calibrate the VTC gain variation. In addition, a 4-bit tunable delay buffer is inserted at the output stage to calibrate the VTC time offset, enhancing the PVT performance. By resizing the push-pull inverters' PMOS/NMOS size ratio in the output buffer chain, the jitter contribution from buffers has been reduced. It also recovers the signal's pulse width consumed during the voltage-time conversion, facilitating the time signal processing following VTC. Designed and fabricated in 28 nm CMOS, the prototype VTC occupies a 0.0012 mm2 active area. Measurement results show that the VTC can run up to 4 GHz at a 0.6 V power supply, achieving -56.4 dB total harmonic distortion (THD) with Nyquist input and consuming 2.1 mW. |
| first_indexed | 2024-10-01T03:18:19Z |
| format | Journal Article |
| id | ntu-10356/165010 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T03:18:19Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | ntu-10356/1650102023-03-10T15:40:12Z A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS Chen, Qian Boon, Chirn Chye Liang, Yuan School of Electrical and Electronic Engineering Kun Gao Xinxin Technologies Pte. Ltd., Singapore Engineering::Electrical and electronic engineering Shrink Sampling Time-Domain Signal Processing A 0.6 V voltage-to-time converter (VTC) has been presented in this work for the emerging energy-efficient time-domain circuits and systems. The proposed VTC supports a rail-to-rail input by leveraging shrink sampling with two cascaded voltage sampling and charge sharing switches, breaking the tradeoff between linearity and input range of the traditional VTC and enabling low voltage operation. The charging current source is adjustable to calibrate the VTC gain variation. In addition, a 4-bit tunable delay buffer is inserted at the output stage to calibrate the VTC time offset, enhancing the PVT performance. By resizing the push-pull inverters' PMOS/NMOS size ratio in the output buffer chain, the jitter contribution from buffers has been reduced. It also recovers the signal's pulse width consumed during the voltage-time conversion, facilitating the time signal processing following VTC. Designed and fabricated in 28 nm CMOS, the prototype VTC occupies a 0.0012 mm2 active area. Measurement results show that the VTC can run up to 4 GHz at a 0.6 V power supply, achieving -56.4 dB total harmonic distortion (THD) with Nyquist input and consuming 2.1 mW. Ministry of Education (MOE) Published version This work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 under Grant MOE2019-T2-1-114. 2023-03-07T07:36:15Z 2023-03-07T07:36:15Z 2022 Journal Article Chen, Q., Boon, C. C. & Liang, Y. (2022). A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS. IEEE Access, 10, 88558-88566. https://dx.doi.org/10.1109/ACCESS.2022.3200678 2169-3536 https://hdl.handle.net/10356/165010 10.1109/ACCESS.2022.3200678 2-s2.0-85137576303 10 88558 88566 en MOE2019-T2-1-114 IEEE Access © 2022 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/. application/pdf |
| spellingShingle | Engineering::Electrical and electronic engineering Shrink Sampling Time-Domain Signal Processing Chen, Qian Boon, Chirn Chye Liang, Yuan A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS |
| title | A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS |
| title_full | A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS |
| title_fullStr | A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS |
| title_full_unstemmed | A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS |
| title_short | A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS |
| title_sort | 0 6 v 4 gs s 56 4 db thd voltage to time converter in 28 nm cmos |
| topic | Engineering::Electrical and electronic engineering Shrink Sampling Time-Domain Signal Processing |
| url | https://hdl.handle.net/10356/165010 |
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