The integration of grounding plane into tsv integrated ion trap for efficient thermal management in large scale quantum computing device
In this work, we demonstrate the addition of grounding plane into the through silicon via (TSV) integrated ion trap to minimize the ion trap heating by effectively shielding the lossy silicon substrate from RF penetration. Windows are made onto this grounding plane to allow the passing through of th...
| Main Authors: | , , , , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2023
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/166181 |
| _version_ | 1826129388781961216 |
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| author | Zhao, Peng Li, Hong Yu Lim, Yu Dian Seit, Wen Wei Guidoni, Luca Tan, Chuan Seng |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Zhao, Peng Li, Hong Yu Lim, Yu Dian Seit, Wen Wei Guidoni, Luca Tan, Chuan Seng |
| author_sort | Zhao, Peng |
| collection | NTU |
| description | In this work, we demonstrate the addition of grounding plane into the through silicon via (TSV) integrated ion trap to minimize the ion trap heating by effectively shielding the lossy silicon substrate from RF penetration. Windows are made onto this grounding plane to allow the passing through of the TSV. CMOS back-end-of-line process on 12-inch wafer platform is used for the trap fabrication. Upon the integration of grounding plane, the on-chip insertion loss is reduced to 0.06 dB (at RF frequency of 50 MHz). Based on the finite element modelling results, for trap with additional grounding plane, the Joule heating-induced temperature rise is reduced from >15 K to 2 K. This work demonstrates the compatibility of grounding plane and TSV in the application of scalable ion trap, enriching the integration toolbox for large scale ion trapping devices. |
| first_indexed | 2024-10-01T07:39:47Z |
| format | Conference Paper |
| id | ntu-10356/166181 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:39:47Z |
| publishDate | 2023 |
| record_format | dspace |
| spelling | ntu-10356/1661812023-04-20T06:02:14Z The integration of grounding plane into tsv integrated ion trap for efficient thermal management in large scale quantum computing device Zhao, Peng Li, Hong Yu Lim, Yu Dian Seit, Wen Wei Guidoni, Luca Tan, Chuan Seng School of Electrical and Electronic Engineering 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) Engineering::Electrical and electronic engineering::Electronic packaging Grounding Plane Heterogenous Integration In this work, we demonstrate the addition of grounding plane into the through silicon via (TSV) integrated ion trap to minimize the ion trap heating by effectively shielding the lossy silicon substrate from RF penetration. Windows are made onto this grounding plane to allow the passing through of the TSV. CMOS back-end-of-line process on 12-inch wafer platform is used for the trap fabrication. Upon the integration of grounding plane, the on-chip insertion loss is reduced to 0.06 dB (at RF frequency of 50 MHz). Based on the finite element modelling results, for trap with additional grounding plane, the Joule heating-induced temperature rise is reduced from >15 K to 2 K. This work demonstrates the compatibility of grounding plane and TSV in the application of scalable ion trap, enriching the integration toolbox for large scale ion trapping devices. National Research Foundation (NRF) This work is supported by the National Research Foundation, Singapore, under its ANR-NRF Joint Grant Call (NRF2020-NRF-ANR037 HIT). 2023-04-20T06:02:14Z 2023-04-20T06:02:14Z 2022 Conference Paper Zhao, P., Li, H. Y., Lim, Y. D., Seit, W. W., Guidoni, L. & Tan, C. S. (2022). The integration of grounding plane into tsv integrated ion trap for efficient thermal management in large scale quantum computing device. 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 137-142. https://dx.doi.org/10.1109/ECTC51906.2022.00032 9781665479431 https://hdl.handle.net/10356/166181 10.1109/ECTC51906.2022.00032 2-s2.0-85134705077 137 142 en NRF2020-NRF-ANR037 HIT © 2022 IEEE. All rights reserved. |
| spellingShingle | Engineering::Electrical and electronic engineering::Electronic packaging Grounding Plane Heterogenous Integration Zhao, Peng Li, Hong Yu Lim, Yu Dian Seit, Wen Wei Guidoni, Luca Tan, Chuan Seng The integration of grounding plane into tsv integrated ion trap for efficient thermal management in large scale quantum computing device |
| title | The integration of grounding plane into tsv integrated ion trap for efficient thermal management in large scale quantum computing device |
| title_full | The integration of grounding plane into tsv integrated ion trap for efficient thermal management in large scale quantum computing device |
| title_fullStr | The integration of grounding plane into tsv integrated ion trap for efficient thermal management in large scale quantum computing device |
| title_full_unstemmed | The integration of grounding plane into tsv integrated ion trap for efficient thermal management in large scale quantum computing device |
| title_short | The integration of grounding plane into tsv integrated ion trap for efficient thermal management in large scale quantum computing device |
| title_sort | integration of grounding plane into tsv integrated ion trap for efficient thermal management in large scale quantum computing device |
| topic | Engineering::Electrical and electronic engineering::Electronic packaging Grounding Plane Heterogenous Integration |
| url | https://hdl.handle.net/10356/166181 |
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